diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index a24281f..0b30724 100644 --- a/riscv-platform-spec.adoc +++ b/riscv-platform-spec.adoc @@ -118,8 +118,22 @@ The M platform has the following extensions: value stored to that location. (That is, the fetched instruction is not an unpredictable value, nor is it a hybrid of the bytes of the old and new values.) -** Platforms is allowed to operate only in little-endian mode i.e. +** When an illegal instruction trap is taken into M-mode, exception- specific + information must be written to the `mtval` CSR. +** When an illegal instruction trap is taken into S-mode, exception- specific + information must be written to the `stval` CSR. +** Platforms are allowed to operate only in little-endian mode i.e. implementations must hardwire the mstatus.MBE field to 0. +** If the RISC-V ISA H-extension is implemented then the OS-A platform must + comply with the following additional requirements: +*** When virtual instruction trap is taken into M-mode, exception- specific + information must be written to the `mtval` CSR. +*** When virtual instruction trap is taken into S-mode, exception- specific + information must be written to the `stval` CSR. +*** When guest page fault is taken into M-mode, exception-specific + information must be written to the `mtval2` CSR. +*** When guest page fault is taken into S-mode, exception-specific + information must be written to the `htval` CSR.
[sidebar] -- @@ -448,9 +462,13 @@ base with the additional requirements as below. ==== Architecture The platforms which conform to server extension are required to implement +
-- RV64 support -- RISC-V H ISA extension -- VMID support +* RV64 support +* RISC-V ISA H-extension with following additional requirements: +** VMID support +*** When load/store/AMO fault is taken into M-mode, transformed standard + instruction must be written to the `mtinst` CSR. +*** When load/store/AMO fault is taken into S-mode, transformed standard + instruction must be written to the `htinst` CSR.
