Re: [PATCH v4 6/6] Follow profile naming as-per latest RISC-V profiles spec
On 09/08/21, 5:06 AM, "Alistair Francis" <Alistair.Francis@...> wrote:
On Sat, 2021-08-07 at 11:43 +0530, Anup Patel wrote:
> We should follow profile naming as-per latest RISC-V profiles
> specification. Also, we should avoid explicit mentions of
> "RV32xxx" and "RV64xxx" ISA strings.
> Signed-off-by: Anup Patel <anup.patel@...>
> riscv-platform-spec.adoc | 37 ++++++++++++++++---------------------
> 1 file changed, 16 insertions(+), 21 deletions(-)
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> index e4a8bdc..f5ba29c 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -35,8 +35,9 @@ toc::
> |RVA22 | RISC-V Application 2022 <<spec_profiles>>
> |EE | Execution Environment
> |OSPM | Operating System Power Management
> -|RV32GC | RISC-V 32-bit general purpose ISA described as
> -|RV64GC | RISC-V 64-bit general purpose ISA described as
> +|RVA22U64 | RISC-V 2022 user-mode profile <<spec_profiles>>
> +|RVA22S64 | RISC-V 2022 supervisor-mode profile <<spec_profiles>>
> +|RVA22M64 | RISC-V 2022 machine-mode profile <<spec_profiles>>
Why do these have 64 at the end?
The "64" at the end means RV64.
> |RAS | Reliability, Availability, and Serviceability
> |CLINT | Legacy Core-Local Interrupt Controller
> |ACLINT | Advanced Core-Local Interrupt Controller
> @@ -97,7 +98,8 @@ The M platform has the following extensions:
> === Base
> ==== Architecture
> * ISA Requirements
> -** The OS-A platform is required to comply with the RVA22 profile
> +** The OS-A platform harts are required to comply with the RVA22U64
> + RVA22S64 profiles <<spec_profiles>>.
> ** Within main-memory regions, aligned instruction fetch must be
> atomic, up to
> the smaller of ILEN and XLEN bits. In particular, if an aligned 4-
> byte word
> is stored with the `sw` instruction, then any processor attempts
> to execute
> @@ -428,9 +430,6 @@ systems.
> discovery mechanism, etc.
> - The requirements are operating system agnostic, specific
> implementation agnostic.
> -- Any RV32GC or RV64GC platform seeking compatibility with the base
> -specification is required to implement all three privilege modes
> i.e. M, S and
> -U mode.
> - For the generic mandatory requirements this base specification
> will refer to
> the EBBR Specification. Any deviation from the EBBR will be
> mentioned in the requirements.
> @@ -478,14 +477,13 @@ mentioned in the requirements.
> // Server extension for OS-A Platform
> === Server Extension
> -The server extension specifies additional requirements for RV64I
> based server
> -class platforms. The server extension includes all of the
> requirements for the
> +The server extension specifies additional requirements for server
> +platforms. The server extension includes all of the requirements for
> base with the additional requirements as below.
> ==== Architecture
> The platforms which conform to server extension are required to
> implement +
> -* RV64 support
> * The `time` CSR must be implemented in hardware
> * The Sstc extension <<spec_priv_sstc>> must be implemented
> * RISC-V ISA H-extension with following additional requirements:
> @@ -545,9 +543,9 @@ additional requirements:
> ==== Boot and Runtime Requirements
> ===== Firmware
> -The boot and system firmware for the RV64I server platforms required
> to be
> -based on UEFI as per the base specification with some additional
> -requirements as mentioned below.
> +The boot and system firmware for the server platforms must support
> UEFI as
> +defined in by the OS-A base platform with some additional
> +described in following sub-setions.
> ====== PCIe support
> The platforms are required to implement
> *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL* and other
> @@ -576,10 +574,10 @@ the base spec requirements.
> ====== ACPI
> -For RV64I server platforms, ACPI tables are required to be passed
> via UEFI
> -to the operating system for the purpose of discovery and the
> configuration of
> -the hardware. This section defines the required ACPI tables and
> objects. All
> -other ACPI tables for RISC-V can be implemented as needed adhering
> to the ACPI
> +For server platforms, ACPI tables are required to be passed via UEFI
> to the
> +operating system for the purpose of discovery and the configuration
> of the
> +hardware. This section defines the required ACPI tables and objects.
> All other
> +ACPI tables for RISC-V can be implemented as needed adhering to the
> spec version 6.4+(RISC-V support when added).
> In ACPI namespace, processors are required to be defined under the
> System Bus
> @@ -963,11 +961,8 @@ although they do not have to in order to meet
> the specification.
> === Base
> ==== Architecture
> -The M Platform specification depends on the RVM22 specification and
> -requirements from RVM22 must be met.
> -Any RISC-V system that uses at least RV32/64G can meet the M
> +The M Platform harts must comply with the RVM22M64 profile
> ==== Interrupt Controller
> Embedded systems are recommended to use a spec compliant PLIC