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  2. Proposal v2: SBI PMU Extension

Re: Proposal v2: SBI PMU Extension

Anup Patel
 

Like Greg already mentioned, SBI PMU event_idx.type == 0x2 is HARDWARE RAW event.

 

To monitor RAW events, user-space perf tool will create user space perf RAW event (i.e. perf_event_attr.type == 4 and perf_event_attr.config = = <hardware_specific_raw_event_idx>). The Linux RISC-V PMU driver will allocate and map matching HARDWARE counter which supports specified corrosponding SBI RAW event (event_idx.type = 2, event_idx.code = perf_event_attr.config[11:0], and event_idx.info = perf_event_attr.config[59:12]).

 

The SBI PMU RAW events are mostly opaque to all software layers (i.e. User-space, Linux, Hypervisors, and OpenSBI). Users will need to refer HW specs for semantics of RAW events when using RAW events with perf tool.

 

Regards,

Anup

 

From: tech-unixplatformspec@... <tech-unixplatformspec@...> On Behalf Of Greg Favor
Sent: 09 July 2020 12:43
To: Brian Grayson <brian.grayson@...>
Cc: Zong Li <zong.li@...>; Anup Patel <Anup.Patel@...>; Atish Patra <Atish.Patra@...>; andrew@...; tech-unixplatformspec@...
Subject: Re: [RISC-V] [tech-unixplatformspec] Proposal v2: SBI PMU Extension

 

I think this need is covered by this excerpt from the v2 proposal:

 

If event_idx.type == 0x2 then it is HARDWARE RAW event. For HARDWARE RAW
event, both event_idx.info and event_idx.code are platform dependent. 

 

Greg 

 

 

On Thu, Jul 9, 2020 at 12:05 AM Brian Grayson <brian.grayson@...> wrote:

My question is, let's say I know that putting the value 0x12345678 into the mhpmevent3 register gets me the event I want, and there is no support for that event in the SBI spec/API. Will this API allow me to program such an event, basically bypassing the usual mapping functionality? perf basically allows you to say "I know this event number is not one you know about, but it's the value I want placed directly into the hardware." I want to ensure that the full capabilities of the hardware will still be accessible through the SBI spec in some sort of "raw" mode, and I didn't see a way for that to happen right now. We don't want to restrict users to the lowest common denominator of functionality.

 

Brian

 

 

On Wed, Jul 8, 2020 at 10:27 PM Zong Li <zong.li@...> wrote:

On Thu, Jul 9, 2020 at 1:06 AM Brian Grayson <brian.grayson@...> wrote:
>
> Would there be a raw style interface to access all the SBI-unaware events, like perf's rNNN support?
>

Follow this question, in our current proposal, s-mode software only
knows the event_idx, and m-mode firmware takes care of the mapping, my
question is that s-mode software doesn't seem to understand the
meaning of each event_idx, that means, it just get the array of all
supported event_idx, but couldn't know which one is for what. This
also happened on u-mode program, for rNNN interface, normally, we
should refer to the processor specific documentation for getting these
details, and now, users won't know what value they should give. Please
correct me if I miss something. Thanks.

> How would this work on a multicore system -- would the SBI calls only handle the current hart's counters? That seems easiest to deal with.
>
> Brian
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