On Thu, 2021-11-04 at 10:21 -0500, Ved Shanbhogue wrote:
On Thu, Nov 04, 2021 at 02:51:23PM +0000, Atish Patra wrote:
On Sun, 2021-10-31 at 14:56 -0500, Vedvyas Shanbhogue wrote:Agree that adding a clarification that these are "required" only if
Same explanation as above. MSWI devices are required only if M-mode
3. Section 220.127.116.11.1 and secttion 18.104.22.168.2 - requirements on M-
"One or more ACLINT MSWI devices are required to support M-
interrupt is required.
We probably can add more clarification around this text to avoid the
confusion so that there are some guidance on MMIO devices for systems
supporting SW interrupts or other interrupts to M-mode is supported.
Else the specification reads as if these are always required.
Sure. I will update the patch.
Could that be clarified. Presently there is only one section for
- "Handle misaligned load and store" - should this be optionalThis is required for base only.
not required. The server extension (section 22.214.171.124)
hardware support for mislaligned accesses.
runtime services and it does not make a distinction between base and
This was added to make sure that supervisor mode software canI dont think the architecture implements CMO CSRs. Perhaps these are
to work for the platforms that did not implements certain CSRs in
hardware. Some of the CSRs that can I think of
2. CMOs (to support Alwinner D1 & beagleV)
3. HTIMEDELTA (if H extension is present)
I was talking about the CMO (cache management operations) CSRs.
Here are the details.https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v0.6.pdf
I feel the requirements could be stated differently. We could list all
CSRs that supervisor mode software requires to be present. Then a
platform may choose to emulate them or implement them in hardware.
Otherwise this requirement to emulate missing CSRs is puzzling because
as a silicon designer or a M-mode firmware designer one is left
wondering what emulations should be implemented.
Agree. That would address the above as well.
On a second thought, we can remove the entire "Required features of
M-Mode runtime also include:" section as M-mode is no longer
ok. I am going to remove the M-mode runtime requirement section.
All of them are implicit anyways.
SBI interface is mandatory. Thus, the M-mode runtime must at leastAgree.
implement SBI v0.3 with specific extensions.
This list of SBI extensions for server extension will change alongThanks. That makes sense.
major changes of removing the extension concept and renaming the base
spec to OS-A embedded.
For the server extension, only the following SBI extension will be
PMU, HSM, SRST
That sounds good to me.
Sure. May be we can include the PCIe snippet in the general note as
5. Section 126.96.36.199.2
The note and the associated implementation note about providing
mechanism controlled by M-mode software could be removed since
there is a more general note in the security section added by
of this set about protecting M-mode assets from I/O agents.
Additionally, I am thinking moving the implementation note to the new
security section would provide more clarity about the requirement
allowing alternate implementation. Any thoughts ?