[PATCH 4/6] Reduce the number of mandatory PMU events.


Last level cache and NUMA node cache events are not specific to per hart.
Do not make them mandatory for per hart performance monitor events.

Signed-off-by: Atish Patra <atishp@...>
riscv-platform-spec.adoc | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 78ceae532f96..8798e71a18e5 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -593,9 +593,10 @@ accesses should not take address misaligned exceptions.
*** The platform must implement all of the general hardware events defined by
the SBI PMU extension.
** Hardware cache events
-*** The platform must implement all of the hardware cache events for READ
-operations while WRITE operation must be implemented for L1D, LL and DTLB
+*** The platform must implement READ operations for all of the hardware cache
+events except SBI_PMU_HW_CACHE_NODE and SBI_PMU_HW_CACHE_LL defined in the SBI
+PMU extension.
+*** Thue platform must implement WRITE operation for L1D, and DTLB caches.


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