- [PATCH 5/6] Add more clarity about privilege mode optionality.
Re: [PATCH 5/6] Add more clarity about privilege mode optionality.
On Thu, Nov 18, 2021 at 11:47 PM Heinrich Schuchardt <xypron.glpk@...
Am 19. November 2021 01:09:33 MEZ schrieb atishp@...:
>The platform spec provides various choices for interrupt controller to
>be implemented in the platform. As M-mode is not a mandatory requirement
>any more and VS-mode is only required for platforms with hypervisor extension,
>the choices should follow that as well.
>Signed-off-by: Atish Patra <atishp@...>
> riscv-platform-spec.adoc | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
>index 8798e71a18e5..81ae740154c1 100644
>@@ -319,7 +319,9 @@ tick for MTIME counter resolution of 10ns.
> The OS-A platform must comply with one of the four interrupt support
> categories described in following sub-sections. The hardware must support at
> least one of the four interrupt categories while software must support all of
>-the interrupt categories described below.
>+the interrupt categories described below. Any hardware requirement for a specific
>+privilege mode is only applicable for a platform only if that privilege mode is
Please, remove one 'only'.
My bad. Fixed it.
>+implemented in the platform.
> ====== Legacy wired IRQs - DEPRECATED
>@@ -367,7 +369,7 @@ devices.
> ** AIA local interrupt CSRs must be supported by each hart.
> *** `siselect` CSR must support holding 9-bit value.
> *** `vsiselect` CSR must support holding 9-bit value.
>-** Per-hart AIA IMSIC devices to support MSIs for M-mode, HS-mode and VS-mode.
>+** Per-hart AIA IMSIC devices are required to support MSIs for M-mode, HS-mode and VS-mode.
> *** Must support IPRIOLEN = 6 to 8.
> *** Must support at least 63 distinct interrupt identities.
> *** Must implement `seteipnum_le` memory-mapped register.
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