OS-A PCIe Questions
I’m new to participating in the platform WG. I’m working at SiFive now. I spent the last 20 years doing PCIe compliant IO fabrics for Intel chipsets.
I have a few comments / questions about the PCIe:
1) section 184.108.40.206: Why are we requiring INTx? We should allow a modern system to be built without the legacy INTx requirements.
2) section 220.127.116.11: A discussion of No_snoop must also include Relaxed Order (RO). When a root port forwards a mix of traffic with NS=0, RO=0 and NS=1 , RO=0. The requirement to enforce ordering tends to lead to ignoring the NS hint and snooping the trarffic anyway.
2) section 18.104.22.168: Why do we exclude the possibility of a Host bridge that supports both RCiEP and Root Ports?