Hello,
I’m new to participating in the platform WG. I’m working at SiFive now. I spent the last 20 years doing PCIe compliant IO fabrics for Intel chipsets.
I have a few comments / questions about the PCIe:
1) section 4.7.3.3: Why are we requiring INTx? We should allow a modern system to be built without the legacy INTx requirements.
2) section 4.7.3.4: A discussion of No_snoop must also include Relaxed Order (RO). When a root port forwards a mix of traffic with NS=0, RO=0 and NS=1 , RO=0. The requirement to enforce ordering tends to lead to ignoring the NS hint and snooping the trarffic anyway.
Proposed text for 4.7.3.4:
A system is required to provide hardware managed coherence for PCIe traffic. A system may ignore the No_snoop hint bit and treat all PCIe traffic as HW coherent. A system may choose to honor the No_snoop (NS) hint bit on incoming PCIe transactions. In this case software must manage coherence for the memory used by the device issuing the transactions. Such systems must also honor the relaxed order (RO) hint bit. To take full advantage of SW coherence the device should set both NS and RO to 1. Otherwise, when RO=0 the snooped and non-snooped traffic arriving through a host bridge must be kept ordered, eliminating the benefit of routing some traffic around the cache hierarchy to memory.
2) section 4.7.3.5: Why do we exclude the possibility of a Host bridge that supports both RCiEP and Root Ports?
Cheers,
Michael.
