On Thu, Jun 23, 2022 at 11:30:28PM +0400, Furquan Shaikh wrote:
Thanks for sending out these ECRs. After looking at these documents,
we have a lot of comments/questions, but I think it might be
productive to walk through the assumptions and approach for defining
these structures over a meeting with interested RISC-V members. What
do you think?
Yes, let's do that. I will setup a meeting on Monday 27th 2022. We can
continue the discussion later if we can not finish in an hour.
On Tue, Jun 21, 2022 at 9:48 PM Sunil V L <sunilvl@...> wrote:
Please review below Engineering Change Request (ECR) to update the ACPI
spec for enabling basic ACPI support for RISC-V.
1) Add INTC structure in MADT Table -
2) Add new RISC-V Hart Capabilities Table (RHCT).
3) Add AIA interrupt controllers in MADT table
First two ECRs do not have a dependency on any RVI specs which are not
frozen. But the third ECR has a dependency on AIA spec to be frozen.
Hence this AIA ECR will NOT be sent to UEFI forum until AIA spec is frozen.
The PoC for these ECRs is complete and ACPI enabled Linux boots on qemu
platform. Below are links to the source code for the PoC.
qemu - https://github.com/ventanamicro/qemu/tree/dev-upstream
edk2 - https://github.com/ventanamicro/edk2/tree/dev-upstream
edk2-platforms - https://github.com/ventanamicro/edk2-platforms/tree/dev-upstream
linux - https://github.com/ventanamicro/linux/tree/dev-upstream
You can find how to build and test these changes in this link -
You can provide the feedback by commenting in the document itself. I am
hoping to send at least first two ECRs to UEFI forum by 8th August 2022.
So, appreciate your help to improve these ECRs before 4th August 2022
(45 days from today).
Feel free to reach out if you have any questions.