Re: Proposal: RISC-V Hypervisor Sync-up Call
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Hi Anup and all,
At my research lab we have:
1. Extended a RISC-V Rocket core per the RISC-V H-extension specification (v 0.6.1);
2. Extended the PLIC to support guest external interrupts;
3. Extended our in-house hypervisor (Bao - https://github.com/bao-project/bao-hypervisor/tree/wip/riscv) with RISC-V hardware virtualization support;
4. Developed a demo of the full system (Rocket + H extension + FreeRTOS + Linux) on a Xilinx ZCU104 FPGA - small video on Twitter:
We are currently focused on benchmarking the full system with cycle-accurate simulation using Firesim.
Happy to participate in the calls and help and/or share our experience in any sense.
On Mon, Aug 31, 2020 at 2:11 PM Anup Patel <anup.patel@...> wrote: