Mirroring (very roughly) ARM SBSA and x86 C-states supported nowadays, I would maybe suggest the following power states between "Run" (aka C0) and "Off" (aka C6).  Only the two "Sleep" states matter to this SBI call, and they are both state-preserving:

- Run                    "C0"

- Idle (i.e. WFI)     "C1"

- Sleep                 "C3 sub-state"

- Deep Sleep        "C3 sub-state"

- Off                      "C6"

Many implementations may support only one Sleep state.  Low-power designs may support both.  (Option for additional "custom" parameter values should also be supported in the SBI call.)

Among these Sleep states, things like switching to a min operational voltage and frequency, switching to a retention voltage, flushing caches, etc. will come into play (as well as shutting off all clocking to the core).  But the actual meaning in a system for these states would be implementation-specific.

 

How does ARMv8 and x86 handle this?  Blindly I would imagine we would do the same.  I'm also guessing the answer is "both DT and ACPI" since some systems use DT and some use ACPI (unless the platform spec standardizes on just one of these).

Greg