Re: [PATCH v1 2/2] Section 3.1.4 System Peripherals.


Mayuresh Chitale
 

------ Original Message ------
From: "Heinrich Schuchardt" <xypron.glpk@...>
To: "Mayuresh Chitale" <mchitale@...>; tech-unixplatformspec@...
Sent: 4/11/2021 9:15:48 PM
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v1 2/2] Section 3.1.4 System Peripherals.

On 4/11/21 5:02 PM, Mayuresh Chitale wrote:
This patch is an initial draft for the section
3.1.4 - System Peripherals.

Signed-off-by: Mayuresh Chitale <mchitale@...>
---
riscv-platform-spec.adoc | 31 +++++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 003181c..f164545 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -52,10 +52,33 @@ include::profiles.adoc[]
* Interrupt Assignments

==== System Peripherals
-* UART/Serial Console
-* Clocks
-* Timers
-* Watchdog Timers
+* *UART/Serial Console* +
+In order to facilitate the bringup and debug of the low level initial platform
+software(firmware, bootloaders, kernel etc), the platform shall implement a UART
+port compatible with PC16550D.
Is software compatibility with PC16550D free of copyright restrictions?
(We should not disallow open hardware.)

Strict PC16550D compatibility would for instance preclude usage of lower
voltages. Is this really needed?
The intention here is to require a 'register compatibility' with 16550 and not so much the phy level compatibility.

Isn't it enough to to have any UART that at least supports 115200,8N1?

Best regards

Heinrich

+* *Clock and Timers* +
+** Platforms shall provide a 10ns resolution 64-bit counter with strictly monotonic updates.
+** The counter shall have a minimum update frequency of 10MHz.
+** Platforms shall implement the time CSR.
+** Platforms shall advertise the timebase to the operating systems via the
+`timebase-frequency` DT property.
+** Platforms shall implement the
+https://lists.riscv.org/g/tech-privileged/message/404[Sstc] extension.
+** Platforms shall delegate the supervisor timer interrupt to 'S' mode and if
+the 'H' extension is implemented, the virtual supervisor timer interrupt to 'VS' mode.
+
+* Watchdog Timers +
+** Platforms shall implement a two stage watchdog timer.
+** The software shall periodically update the watchdog stage 1 value to a
+future moment.
+** If the mtime/time increments past the watchdog stage 1 compare value then an
+interrupt shall be raised and routed to a RISC V hart and the watchdog stage 2
+shall be activated.
+** If the mtime/time increments past the watchdog stage 2 compare value an
+interrupt shall be raised and routed to an external hardware unit such as a
+BMC to affect a system reset. If the watchdog stage1 compare value was updated
+before such an event occurred then the watchdog stage 1 interrupt shall be
+deasserted and the watchdog stage 2 shall be deactivated.

==== Boot Process
* Firmware

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