On Thu, 2020-06-04 at 15:34 +0300, David Abdurachmanov wrote:

Atish,

Could I circulate WebEx meeting information to people outside RISC-V
Foundation? In particular I would like to see if we could get
engineers from Red Hat, SUSE and Canonical to join. Red Hat is a
member of foundation so that's probably an easy answer.

Yeah. I would love to allow anybody (RISC-V foundation member or not)
to jump into the discussions. However, foundation has strict rules on
who can participate in the working group meetings. That's why I
couldn't send the meeting invite to the public mailing list.

Anybody who
is a member can join. If their organization is already a member, they
just need to sign up using the org's email address or they can sign up
as an individual member (I think it's free to be an individual member
now).

david

On Wed, Jun 3, 2020 at 4:08 AM Atish Patra <atish.patra@...>
wrote:

Hi All,
I would like to start a thread to discuss the topics that should go
into the unix platform specification apart from SBI & PLIC. SBI
specification is already tagged as v0.2 & PLIC specification will
follow.

Here is the current version if unix platform specification.


https://github.com/riscv/riscv-platform-specs/blob/master/riscv-unix.adoc

I think the spec definitely needs to have a lot more content than
it
currently has :)

Here are some suggestions. This is just a small list that I can
think
of right now. I am pretty sure we need to have more
sections/subsections with more details.

1. Register state requirement:
- S-mode CSR state before entering to S-mode
- GPR state before entering to S-mode (e.g a0 must contain
hartid, a1 must contain DT address)

2. Runtime firmware requirement:
- Platform runtime firmware must implement SBI v0.2
specification. We can avoid legacy implementations in
future if we
make this mandatory now. But, I am open to
other suggestions
as well.
- RISC-V ISA allows hardware not to implement misaligned
load/store. platform runtime firmware must implement it if it
is not implemented in hardware.
- TIME csr emulation support if not implemented in HW
- HTIMEDELTA csr emulation support (for platforms
with hypervisor support)
- This section can link to the SBI specification.

3. Memory requirement
- DRAM start address
- memory model supported
- Boot address alignment requirement (2MB/4MB for
64bit/32bit)
- other requirement ?

4. Interrupt requirement
- What should be PLIC state upon entering S-mdoe
- Can link to the PLIC specifications
- local interrupt controller (CLIC/CLINT) ?

5. I/O devices ?

I am hoping this can initiate the discussion and we can continue
that
during the working group meetings as well. The next platform
specification working group is scheduled on 9th June(06/09) 8AM
PST.

FYI: The meeting webex link is available in calendar. Let me know
if
you have any issues accessing that.


--
Regards,
Atish

--
Regards,
Atish