On Sun, 2021-04-11 at 20:32 +0530, Mayuresh Chitale wrote:
This patch is an initial draft for the section
3.1.4 - System Peripherals.
Signed-off-by: Mayuresh Chitale <mchitale@...>
riscv-platform-spec.adoc | 31 +++++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 003181c..f164545 100644
@@ -52,10 +52,33 @@ include::profiles.adoc
* Interrupt Assignments
==== System Peripherals
-* UART/Serial Console
-* Watchdog Timers
+* *UART/Serial Console* +
+In order to facilitate the bringup and debug of the low level
+software(firmware, bootloaders, kernel etc), the platform shall
implement a UART
+port compatible with PC16550D.
+* *Clock and Timers* +
+** Platforms shall provide a 10ns resolution 64-bit counter with
strictly monotonic updates.
+** The counter shall have a minimum update frequency of 10MHz.
+** Platforms shall implement the time CSR.
+** Platforms shall advertise the timebase to the operating systems
+`timebase-frequency` DT property.
+** Platforms shall implement the
+** Platforms shall delegate the supervisor timer interrupt to 'S'
mode and if
+the 'H' extension is implemented, the virtual supervisor timer
interrupt to 'VS' mode.
+* Watchdog Timers +
+** Platforms shall implement a two stage watchdog timer.
As the base specification also targets the dev boards, academia FPGAs
at least for Linux 2022, do we need to mandate a watchdog timer.
May be put it as strongly recommended and mandate it in Linux 2024
+** The software shall periodically update the watchdog stage 1 value
+** If the mtime/time increments past the watchdog stage 1 compare
value then an
+interrupt shall be raised and routed to a RISC V hart and the
watchdog stage 2
+shall be activated.
+** If the mtime/time increments past the watchdog stage 2 compare
+interrupt shall be raised and routed to an external hardware unit
such as a
+BMC to affect a system reset.
Is it only intended for server extension as BMCs are common in servers
? We may need to clarify what happens in absence of a BMC ?
If the watchdog stage1 compare value was updated
+before such an event occurred then the watchdog stage 1 interrupt
+deasserted and the watchdog stage 2 shall be deactivated.
==== Boot Process