Re: [PATCH V2 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform


Mayuresh Chitale
 


Thanks,
Mayuresh.


On Thu, May 6, 2021 at 5:58 PM <renba.chang@...> wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure if this
  overlaps with your text or not (The timer setion). I can remove this
  if you prefer to put this with your patch.
Based on the discussion earlier, I thought this would be a separate spec. But it does not overlap with the other text in that section.
- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 84 ++++++++++++++++++++++------------------
 1 file changed, 47 insertions(+), 37 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..0e89fcd 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,14 +49,54 @@ include::profiles.adoc[]
 * Start Address

 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local interrupt
+sources supported by PLIC and how does each of them connect to the hart context
+is PLIC core implementation-specific. +
+(Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== CLINT[[CLINT]]
+On the contrast to PLIC, the Core Local Interrupt (CLINT) provides facilities to trigger local interrupt of <<MachineModeTimer,Machine mode timer>> to hart.
Do we need to refer to CLINT? Would it suffice to describe the memory layout that is compatible with CLINT? 
+
+===== Interrupt Assignments

 ==== System Peripherals
 * UART/Serial Console
 * Clocks
 * Timers
+
+===== Machine Mode Timer[[MachineModeTimer]]
+Machine mode timer is requried for Linux-2022 platform and incorportate with CLINT
+for the locol interrupt to hart.
The format of the operation parameters (`mtime`
+and `mtimecmp` registers) must compliant with RISC-V Privilege specification section 3.1.10.
+The base address of the memory map registers of Machine mode timer is platform
+plementation-specific, however the offset of `mtime` and `mtimecmp` registers
+are fixed as below,
Typos:  locol --> local, incorportate --> incorporate, plementation-->implementation 
+
+.Registers layout of mtimecmp
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
+|`0x4000` |mtimecmp for hart 0 |mtimecmp low for hart 0
+|`0x4004` ||mtimecmp high for hart 0
+|`0x4008` |mtimecmp for hart 1 |mtimecmp low for hart 1
+|`0x400c` ||mtimecmp high for hart 1
+|... ||
+|`0xbff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
+|`0xbff4` ||mtimecmp high for hart 4094
+|=======
+
+.Registers layout of mtime
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
+|`0xbff8` |mtime|mtime low
+|`0xbffc` ||mtime high
+|=======
 * Watchdog Timers

 ==== Boot Process
@@ -289,8 +329,7 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
 specification.

 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant <<PLIC,PLIC>>, a spec compliant
 https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.

@@ -303,38 +342,9 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller and still
 call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must be
-implemented. The two registers must be memory mapped as required by the RISC-V
-specification.
-
-The Embedded-2022 specification requires that the registers be mapped
-adjacent to each other with the `mtime` region at the lower address.
-
-The starting address of this region can be located anywhere in
-memory, including inside other peripherals, as long as the start address is
-4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
----------------------------
+==== Machine Mode Timer
+The Embedded-2022 specification requires RISC-V <<MachineModeTimer,Machine mode timer>> to
+be implemented and incorporated with the Core Local Interrupt (<<CLINT, CLINT>>).

 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM) start at
--
2.19.0.windows.1

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