Re: [PATCH V3 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform


Alistair Francis
 

On Sun, 2021-05-09 at 22:23 -0400, Jonathan Behrens wrote:
I'd expect there could also be a category of "not required by this
version of the platform spec, but will be required in the next one".
But we don't want it required in the next one either.

The idea is to allow vendors to be flexible and share IP between their
current ISA offering and thir RISC-V chips. Look at the latest
Espressif RISC-V MCU for example. While also encouraging new products
to follow a common RISC-V layout if possible.

Alistair


On Sun, May 9, 2021 at 9:33 PM Kumar Sankaran via lists.riscv.org <
ksankaran=ventanamicro.com@...> wrote:
On Sun, May 9, 2021 at 5:45 PM Alistair Francis <
alistair.francis@...> wrote:
On Fri, 2021-05-07 at 09:25 -0700, Greg Favor wrote:
I notice many uses of the word "recommend".  My understanding
is
that
there should be no recommendations in the platform spec - just
requirements.  (To be more precise, I believe the Platforms
Policy
doc puts non-normative content in separate chapters.)
Why are we removing recommendations?

For the embedded spec we don't want to force vendors to meet
certain
requirements if they have a good reason not to. For example if
they
share IP or memory maps across different product lines we want to
allow
that. As that will make it easier for them and their customers to
transition to RISC-V.

On the other hand if vendors are picking addresses or IP we want
to
encourage them to use a standard. Hence the recommendations.

Alistair

The goal is to have a minimal set of requirements that define a
platform as part of the platform spec. Hence, only required
features will be explicitly stated in the spec. If we allow the
flexibility of "optional" or "recommended" features,
platform vendors will end up not implementing them while claiming
compatibility, while at the same time fewer others will implement
them; overall fragmenting the eco-system.
So we should strive to make all recommendations as "Required" to
the extent possible while removing all other non-required features
out of the spec.
 

Greg


On Fri, May 7, 2021 at 9:01 AM Abner Chang
<renba.chang@...>
wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022
platform.

Is this what we want to see of CLINT/Machine mode timer in
the
platform spec?

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not
sure
if
this
  overlaps with your text or not (The timer setion). I can
remove
this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System
Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt
Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 88 +++++++++++++++++++++++-------
--
----
--
--
 1 file changed, 50 insertions(+), 38 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-
spec.adoc
index 160c74a..91c2abb 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,14 +49,56 @@ include::profiles.adoc[]
 * Start Address

 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides
facilities
to route
+the non-local interrupts to the external interrupt of a hart
context
+with a given privilege mode in a given hart. The number of
non-
local
interrupt
+sources supported by PLIC and how does each of them connect
to
the
hart
+context is PLIC core implementation-specific. +
+(Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
PLIC Specification]
+for the implementation reference of PLIC operation
parameters)
+
+===== CLINT[[CLINT]]
+On the contrast to PLIC, the Core Local Interrupt (CLINT)
provides
+facilities to trigger local interrupt of
<<MachineModeTimer,Machine
mode timer>>
+to hart.
+
+===== Interrupt Assignments

 ==== System Peripherals
 * UART/Serial Console
 * Clocks
 * Timers
+
+===== Machine Mode Timer[[MachineModeTimer]]
+Machine mode timer is required for Linux-2022 platform and
incorporate with
+CLINT for the local interrupt to hart. The format of the
operation
parameters
+(`mtime` and `mtimecmp` registers) must compliant with RISC-
V
Privilege
+specification section 3.1.10. The base address of the memory
map
registers
+of Machine mode timer is platform implementation-specific,
however
the offset
+of `mtime` and `mtimecmp` registers are fixed as below,
+
+.Registers layout of mtimecmp
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte)
for
RV32*
+|`0x4000` |mtimecmp for hart 0 |mtimecmp low for hart 0
+|`0x4004` ||mtimecmp high for hart 0
+|`0x4008` |mtimecmp for hart 1 |mtimecmp low for hart 1
+|`0x400c` ||mtimecmp high for hart 1
+|... ||
+|`0xbff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
+|`0xbff4` ||mtimecmp high for hart 4094
+|=======
+
+.Registers layout of mtime
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte)
for
RV32*
+|`0xbff8` |mtime|mtime low
+|`0xbffc` ||mtime high
+|=======
 * Watchdog Timers

 ==== Boot Process
@@ -289,9 +331,8 @@ Any RISC-V system that uses at least
RV32/64G
can
meet the Embedded-2022
 specification.

 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec
compliant
-
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>, a spec
+compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.

 If using just a PLIC the system must continue to use the
original
basic
@@ -303,38 +344,9 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt
controller
and
still
 call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and
`mtimecmp`)
must be
-implemented. The two registers must be memory mapped as
required
by
the RISC-V
-specification.
-
-The Embedded-2022 specification requires that the registers
be
mapped
-adjacent to each other with the `mtime` region at the lower
address.
-
-The starting address of this region can be located anywhere
in
-memory, including inside other peripherals, as long as the
start
address is
-4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a
single
hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
----------------------------
+==== Machine Mode Timer
+The Embedded-2022 specification requires RISC-V
<<MachineModeTimer,Machine mode timer>>
+to be implemented and incorporated with the Core Local
Interrupt
(<<CLINT, CLINT>>).

 ==== Memory Map
 It is recommended that main memory and loadable code (not
ROM)
start
at




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