Re: [PATCH v3 2/2] System Peripherals: Linux 2022 Base spec and server extension

Mayuresh Chitale

On Mon, May 17, 2021 at 8:32 PM Jonathan Behrens <behrensj@...> wrote:
> +** Platforms are required to provide atleast a 10ns resolution 64-bit counter

nit: "at least a" => "an at least" (the former could be misunderstood as saying to have to provide an exactly 10ns timer, but can also provide other timers if you want)

Thanks. I will correct it.

On Mon, May 17, 2021 at 10:20 AM Mayuresh Chitale via <> wrote:
Base spec:
- Clock and Timers

Server extension:
- Clock and Timers

Signed-off-by: Mayuresh Chitale <mchitale@...>
 riscv-platform-spec.adoc | 44 +++++++++++++++++++++++++++++++++++++---
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..328b1dc 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -55,9 +55,40 @@ include::profiles.adoc[]

 ==== System Peripherals
 * UART/Serial Console
-* Clocks
-* Timers
-* Watchdog Timers
+In order to facilitate the bringup and debug of the low level initial platform
+software(firmware, bootloaders, kernel etc), platforms are required to
+implement a UART port which confirms to the following requirements:
+* The UART register addresses are required to be aligned to 4 byte boundaries.
+If the implemented register width is less than 4 bytes then the implmented
+bytes are required to be mapped starting at the smallest address.
+* The UART port implementation is required to be register-compatible with one
+of the following:
+** UART 16550 - _REQUIRED_
+** UART 8250 - _DEPRECATED_
+* Clock and Timers
+** Platforms are required to provide atleast a 10ns resolution 64-bit counter
+with strictly monotonic updates.
+** The hardware clock that drives the counter is required to operate at a minimum
+frequency of 10MHz.
+** Platforms that use DT for hardware discovery are required to advertise the
+timebase to the operating systems via the `timebase-frequency` property of the
+"/cpus" node
+[underline]*_Implementation Note_*
+For a counter with 10ns resolution the `timebase-frequency` value would be 100000000
+(100 MHz) which would also be the minimum possible value for `timebase-frequency`.
+From the software perspective a unit increment of the mtime value would correspond
+to a 10ns interval. However the hardware clock driving the counter could operate at a
+lower frequency, thereby incrementing the mtime value by more than one unit per
+clock tick.

 ==== Boot Process
 * Firmware
@@ -246,6 +277,13 @@ implemented but it can return EFI_UNSUPPORTED.

 ==== System Peripherals
+* Clock and Timers
+** Platforms are required to implement the time CSR.
+** Platforms are required to implement the
+[Sstc] extension.
+** Platforms are required to delegate the supervisor timer interrupt to 'S'
+mode. If the 'H' extension is implemented then the platforms are required to
+delegate the virtual supervisor timer interrupt to 'VS' mode.
 * PCI-E

 ==== Secure Boot

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