Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
toggle quoted message Show quoted text
Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this require change in Table-1 privilege mode accesses? as well?
Should there also be a suggestion/recommendation on how to disable a pending interrupt (typically by writing to mtimecmp)?
On Thu, May 27, 2021 at 10:45 AM Anup Patel <anup.patel@...> wrote: