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Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Greg Favor
 

On Thu, May 27, 2021 at 10:34 AM Neel Gala <neelgala@...> wrote:
Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this require change in Table-1 privilege mode accesses? as well?

Architecturally the 'time' CSR reads the same concept of "time" as the 'mtime' register.  Simplistically the RDTIME pseudoinstruction reads what is in the 'mtime' register.  One implementation is that each hart has a local copy of 'mtime' that is available to be read by RDTIME (in other words, copies of 'mtime' are distributed in hardware to each hart - to appear as the 'time' CSR inside each hart).  Another implementation is to trap and emulate RDTIME using a read of the memory-mapped 'mtime' register.  Other implementation approaches are possible.

Greg

Should there also be a suggestion/recommendation on how to disable a pending interrupt (typically by writing to mtimecmp)?
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