1. Messages
  2. [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Greg Favor
 

On Fri, May 28, 2021 at 2:44 PM Josh Scheid <jscheid@...> wrote:
One other issue with the "mtime" synchronization by SW approach is that this effectively places an upper limit on the achievable timer unit resolution.  It'd be some equation based on the ordered access latency of the reference and target resources, perhaps.

Has this been explicitly considered?  What is the expected upper limit and where should the platform be moving towards in the future?  Would further work be needed to enable >=1GHz timer resolution?

More recent ARM SBSA requires a 1 GHz counter resolution, but does not place any requirement on the actual measurable 'time" resolution (i.e. a minimum update frequency).  So one can have 1 ns resolution in the 'time' counter value, but the actual measurable granularity could be just 1 us.

Upping the standard counter resolution seems of little or secondary value.  It's the actual maximum granularity or resolution of measurable time that matters.  Which no one in RISC-V (or ARM SBSA) seems willing or wanting to require actual 1 ns resolution to time measurements.

Greg
Join {tech-unixplatformspec@lists.riscv.org to automatically receive all group messages.