Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
You first question is already answered by Greg.
Regarding second question/suggestion, I agree we should explicitly state how to disable a pending interrupt.
From: tech-unixplatformspec@... <tech-unixplatformspec@...> On Behalf Of Neel Gala
Sent: 27 May 2021 23:05
To: Anup Patel <Anup.Patel@...>
Cc: Josh Scheid <jscheid@...>; tech-aia@...; tech-unixplatformspec@...; Atish Patra <Atish.Patra@...>; Greg Favor <gfavor@...>; Alistair Francis <Alistair.Francis@...>; Andrew Waterman <andrew@...>; John Hauser <jh.riscv@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this require change in Table-1 privilege mode accesses? as well?
Should there also be a suggestion/recommendation on how to disable a pending interrupt (typically by writing to mtimecmp)?
On Thu, May 27, 2021 at 10:45 AM Anup Patel <anup.patel@...> wrote: