Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Greg Favor

On Sun, May 30, 2021 at 5:15 AM Anup Patel <Anup.Patel@...> wrote:

Regarding second question/suggestion, I agree we should explicitly state how to disable a pending interrupt.

More properly, this should be a non-normative sentence added to the Machine Timer Registers section in the Priv spec - that notes that setting mtimecmp to the max value effectively disables generation of a timer interrupt.



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