I'm not sure if an IOPMP could be used for this particular purpose, but more generally IOPMP is being driven by embedded people and isn't consciously thinking about functionality requirements implied

The proposal allows for prefetchable BARs to be programmed to support as I/O or Memory. This seems to conflict with the priv spec that states: """ Memory regions that do not fit into regular main

Is this an M-mode SW requirement or a HW requirement that these interrupts are delegatable (writeable) in HW? Why require the delegation by M-mode instead of allowing for M-mode to trap and pass down?

While potentially a fine goal, it seems that to make this happen in a manner that allows Platform-compliant SW to be portable, more needs to be done beyond the Zicmobase work, at least in terms of

I have already sent questions to Andrew to get the official view as to the intent of this aspect of the Priv spec and what is the proper way or perspective with which to be reading the ISA specs.

If this is an issue with the priv spec please add it to the priv spec github issues. thanks Mark

Priv: """ Accesses by one hart to main memory regions are observable not only by other harts but also by other devices with the capability to initiate requests in the main memory system (e.g.,

We had quite a bit of discussion about SBI versioning in past when we were drafting SBI v0.2 specification. The conclusion of those discussions was: We certainly needed a version for SBI

Hi All, The next platform HSC meeting is scheduled on Mon Jun 14th at 8AM PST. Here are the details: Agenda and minutes kept on the github

Hi All, The slides from today's AIA meeting are here: https://docs.google.com/presentation/d/1WHGm7ZpOkVlk_sAVYVU5UwBXt1cdH-8fM1s2vdpY6K4/edit?usp=sharing Both AIA and ACLINT specifications are now

Thanks. I will fix this and the typos below in the next version. Yes, ACPI is mandatory for server extension. I am not sure if we have a standard mechanism yet.

<mchitale@...> wrote: nits: 2 SoB here Is ACPI mandatory? at least Is this mechanism a standard one, or platform specific? at least typo: implement typo: access typo:

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> Signed-off-by: Mayuresh Chitale <mchitale@...> ---

This is an initial patch for PCIe requirements for the server extension. The goal is to specify requirements for those PCIe elements which interact with the system such as PCIe config space, memory

One thing that I'd like to see resolved for the 0.3 release is a precise specification for what sbi_probe_extension does. Right now the description says "Returns 0 if the given SBI extension ID (EID)

We have tagged the current SBI specification as a release candidate for v0.3[1]. It is tagged as v0.3-rc1 which includes few new extensions and cosmetic changes of the entire specification. Here is a

Thanks. Reviewed-by: Atish Patra <atish.patra@...> -- Regards, Atish

Mention that an SBI extension shall not be partially implemented. Signed-off-by: Bin Meng <bmeng.cn@...> --- Changes in v2: - %s/a SBI/an SBI - reword the clarification riscv-sbi.adoc | 6

Hi Atish, Okay, I will send v2. Regards, Bin

Acked-by: Alistair Francis <alistair.francis@...> Alistair