What the sentence is actually referring to is the following: The first watchdog timeout is based on a first programmable timeout period, and the second watchdog timeout is based on a second

Mayuresh Chitale <mchitale@...> 於 2021年7月7日 週三 上午1:42寫道： Does it mean the second-stage watchdog timer would be timeout 1 second after the first-stage watchdog timer has not been

We have released SBI specification v0.3.0[1]. It's been month since the release candidate (v.0.3-rc1). There were only includes few typo fixes and license update patches after that. That's why, we

Actually it is present in the 'Required ACPI System Description Tables'. I can add a pointer to that table in the text above. I will rephrase all instances of this as Greg mentioned in his latest

This patch describes requirements for the watchdog timer for the server extension. Signed-off-by: Greg Favor <gfavor@...> Signed-off-by: Mayuresh Chitale <mchitale@...> ---

The proposed RISC-V name for this memory type is "IO", but it is up in the air for the moment as to whether the the memory types supported by Svpbmt will have acronym names (i.e. IO and NC), or just

From: Abner Chang <abner.chang@...> Signed-off-by: Abner Chang <abner.chang@...> --- contributors.adoc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/contributors.adoc

From: Abner Chang <abner.chang@...> In V2: Change the section to System Real-time and rephrase the content. In V1: Real-time clock is the server basic system peripheral to provide the

Atish Patra <Atish.Patra@...> 於 2021年7月2日 週五 上午2:40寫道： Added to spec. Merged to riscv-plic-spec with Atish and Alistair's Reviewed-by. Abner

From: Abner Chang <abner.chang@...> Signed-off-by: Abner Chang <renba.chang@...> Signed-off-by: Abner Chang <abner.chang@...> --- contributors.adoc | 3 ++- 1 file changed, 2

From: Abner Chang <abner.chang@...> Initial version of Interrupt Controller, Software Interrupt, and Timer Requirements. This patch combines the text sent out by Kumar and the patch Abner sent

From: Abner Chang <abner.chang@...> In V2: - Update Interrupt Controller table in platform spec. - Add comma before Abner Chang in the contributors list. In V1: Initial version of

MCFG table was not referenced earlier. UC is not present in abbreviation section. Moreover, PMA + PBMT seems bit ambiguous to me. It wouldn't hurt to be more verbose here. same comment as

Looks good.Reviewed-by: Abner Chang <abner.chang@...> Mayuresh Chitale <mchitale@...> 於 2021年7月2日 週五 上午12:50寫道：

I think it will be good to provide additional clarification in the beginning about the number of interrupts/contexts. Something along the lines: The PLIC specification supports up-to 1024 interrupts

Reviewed-by: Atish Patra <atish.patra@...> -- Regards, Atish

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 174

V2: - Fixed abbreviation for root complex integrated endpoint - Added section for PCIe device firmware requirement. V1: - Initial patch. Mayuresh Chitale (1): server extension: PCIe requirements

Updated v2 of the cache coherency patch Changes from v1 Brought in all cache coherency changes after feedback Removed ASID requirements diff --git a/riscv-platform-spec.adoc

Sure. Yes, I will fix in the next revision. Yes, looks like I missed it. I will include it in the next revision.