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Re: [PATCH v5 1/8] Additional requirements for H-extension
You are right, we can’t say exception specific non-zero value here.
Also, same is true for virtual instruction trap as well.
Let me quickly re-phrase this.
Regards,
Anup
From:
You are right, we can’t say exception specific non-zero value here.
Also, same is true for virtual instruction trap as well.
Let me quickly re-phrase this.
Regards,
Anup
From:
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By
Anup Patel
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#1277
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Re: [PATCH v5 8/8] Simplify the timer support for the M platform
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
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By
atishp@...
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#1276
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Re: [PATCH v5 7/8] Don't remove images in make clean
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
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By
atishp@...
·
#1275
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Re: [PATCH v5 6/8] Follow profile naming as-per latest RISC-V profiles spec
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
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By
atishp@...
·
#1274
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Re: [PATCH v5 4/8] Re-write the interrupts and timer section
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
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By
atishp@...
·
#1273
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Re: [PATCH v5 1/8] Additional requirements for H-extension
+** When an illegal instruction trap is taken into S-mode, exception-specific
+ non-zere value must be written to the `stval` CSR.
nit: When the illegal instruction is c.unimp (encoded as 0x0000)
+** When an illegal instruction trap is taken into S-mode, exception-specific
+ non-zere value must be written to the `stval` CSR.
nit: When the illegal instruction is c.unimp (encoded as 0x0000)
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By
Jonathan Behrens <behrensj@...>
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#1272
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[PATCH v5 8/8] Simplify the timer support for the M platform
Instead of describe the machine-level timer for the M platform,
we should simply point to the RISC-V ACLINT MTIMER defined by
the RISC-V ACLINT specification.
Signed-off-by: Anup Patel
Instead of describe the machine-level timer for the M platform,
we should simply point to the RISC-V ACLINT MTIMER defined by
the RISC-V ACLINT specification.
Signed-off-by: Anup Patel
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By
Anup Patel
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#1271
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[PATCH v5 7/8] Don't remove images in make clean
The image files (i.e. PNG files) are committed in the repo so
we should not remove it when doing "make clean".
Signed-off-by: Anup Patel <anup.patel@...>
---
Makefile | 1 -
1 file changed, 1
The image files (i.e. PNG files) are committed in the repo so
we should not remove it when doing "make clean".
Signed-off-by: Anup Patel <anup.patel@...>
---
Makefile | 1 -
1 file changed, 1
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By
Anup Patel
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#1270
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[PATCH v5 6/8] Follow profile naming as-per latest RISC-V profiles spec
We should follow profile naming as-per latest RISC-V profiles
specification. Also, we should avoid explicit mentions of
"RV32xxx" and "RV64xxx" ISA strings.
Signed-off-by: Anup Patel
We should follow profile naming as-per latest RISC-V profiles
specification. Also, we should avoid explicit mentions of
"RV32xxx" and "RV64xxx" ISA strings.
Signed-off-by: Anup Patel
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By
Anup Patel
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#1269
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[PATCH v5 5/8] Minor cosmetic changes in SBI section of OS/A-base platform
We don't need a table for required SBI extensions and UEFI interfaces
implemented by UEFI firmware.
Signed-off-by: Anup Patel <anup.patel@...>
Reviewed-by: Alistair Francis
We don't need a table for required SBI extensions and UEFI interfaces
implemented by UEFI firmware.
Signed-off-by: Anup Patel <anup.patel@...>
Reviewed-by: Alistair Francis
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By
Anup Patel
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#1268
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[PATCH v5 4/8] Re-write the interrupts and timer section
We re-write the interrupts and timer section to align the interrupts
and timer table. We also add more fine grained requirements for AIA.
Signed-off-by: Anup Patel <anup.patel@...>
---
Makefile
We re-write the interrupts and timer section to align the interrupts
and timer table. We also add more fine grained requirements for AIA.
Signed-off-by: Anup Patel <anup.patel@...>
---
Makefile
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By
Anup Patel
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#1267
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[PATCH v5 3/8] Move terminology and specifications tables to correct location
The terminology table should be at start and specification table
should be at the end. Also, specification table should be replaced
with bibliography reference list.
Signed-off-by: Anup Patel
The terminology table should be at start and specification table
should be at the end. Also, specification table should be replaced
with bibliography reference list.
Signed-off-by: Anup Patel
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By
Anup Patel
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#1266
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[PATCH v5 2/8] Update terminology and specification tables
This patch updates terminology and specification table in
following ways:
1) Provide complete expansion of terms for APLIC and ACLINT
2) Add links to unprivileged and privileged specifications
3) Add
This patch updates terminology and specification table in
following ways:
1) Provide complete expansion of terms for APLIC and ACLINT
2) Add links to unprivileged and privileged specifications
3) Add
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By
Anup Patel
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#1265
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[PATCH v5 1/8] Additional requirements for H-extension
To have a meaningful H-extension support, both OS/A-base and
OS/A-server platforms must comply with additional requirements
for H-extension.
Also, the little-endian requirement in OS/A-base should
To have a meaningful H-extension support, both OS/A-base and
OS/A-server platforms must comply with additional requirements
for H-extension.
Also, the little-endian requirement in OS/A-base should
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By
Anup Patel
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#1264
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Re: [PATCH v4 6/6] Follow profile naming as-per latest RISC-V profiles spec
On 10/08/21, 12:11 AM, "Atish Patra" <Atish.Patra@...> wrote:
Here are more details on profile naming convention
https://github.com/riscv/riscv-profiles/blob/master/profiles.adoc
On 10/08/21, 12:11 AM, "Atish Patra" <Atish.Patra@...> wrote:
Here are more details on profile naming convention
https://github.com/riscv/riscv-profiles/blob/master/profiles.adoc
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By
Anup Patel
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#1263
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Re: [PATCH v4 6/6] Follow profile naming as-per latest RISC-V profiles spec
On 09/08/21, 5:06 AM, "Alistair Francis" <Alistair.Francis@...> wrote:
Why do these have 64 at the end?
The "64" at the end means RV64.
Regards,
Anup
Alistair
On 09/08/21, 5:06 AM, "Alistair Francis" <Alistair.Francis@...> wrote:
Why do these have 64 at the end?
The "64" at the end means RV64.
Regards,
Anup
Alistair
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By
Anup Patel
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#1262
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Re: [PATCH v4 1/6] Additional requirements for H-extension
I think we should move the requirement to OS-A base and clearly state that non-zero exception specific information should be written to mtinst or htinst.
Regards,
Anup
From:
I think we should move the requirement to OS-A base and clearly state that non-zero exception specific information should be written to mtinst or htinst.
Regards,
Anup
From:
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By
Anup Patel
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#1261
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Re: [PATCH v4 2/6] Update terminology and specification tables
Yes, both the ACLINT and PLIC specs need to go through the process ASAP of becoming approved standards. Obviously that can overlap with the process for the platform specs, but we should get both
Yes, both the ACLINT and PLIC specs need to go through the process ASAP of becoming approved standards. Obviously that can overlap with the process for the platform specs, but we should get both
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By
Greg Favor
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#1260
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Re: [PATCH v4 6/6] Follow profile naming as-per latest RISC-V profiles spec
The above adoc is very tentative and hasn't been reviewed at all. Even Krste would acknowledge that the naming details will change.
So whatever we use in the platform specs is just a placeholder that
The above adoc is very tentative and hasn't been reviewed at all. Even Krste would acknowledge that the naming details will change.
So whatever we use in the platform specs is just a placeholder that
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By
Greg Favor
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#1259
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Re: [PATCH v4 1/6] Additional requirements for H-extension
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish
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By
atishp@...
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#1258
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