Hi All, This is a reminder that we'll be having the OS-A SEE meeting on October 4th at 9am Pacific Time. The join link is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Also,

The `trig_idx` is intentionally a logical index so that Hypervisors can share the debug triggers between guest and host. As an example, you can look at `counter_idx` defined by SBI PMU extension which

Anup Patel <apatel@...> 于2022年7月14日周四 17:39写道： If I understand correctly, the N here should refer to the logical trigger, not the physical number. sbi needs to maintain

You're right. There is a proposal at https://lists.riscv.org/g/sig-hypervisors/message/151 that will likely be implemented by Syntacore before the end of the year. Tim

To implement hardware breakpoints and watchpoints on the riscv, the trigger in M mode is required. We need an sbi extension for debugging to set the trigger. Please give suggestions and

I declared failure on my part. I'll schedule something early next week (unless people think we can squeeze something in tomorrow or Thurs - appears to be a lot conflicts, though). My apologies for

Hi All, Ved let me know I accidentally had a Google Meet Invite link. The Zoom meeting id is: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Thanks. -Aaron

Hi All, We had our first meeting this past Monday (2022/09/12). I pushed the notes to GitHub. As a reminder each group in RVI has their own folder for stashing collateral. For OS-A SEE TG, the folder

<tianshi.xty=alibaba-inc.com@...> wrote: This case is already handled by ACLINT device tree bindings. We just need two separate MTIMER DT nodes where the mtimecmp base address will be

That makes sense, but it does mean that discovery gets more complicated, and (maybe) you need to build separate device trees for each. But maybe that has to happen anyway? I don't know if DT can be

I think this description is better. Assume there are two clusters，each cluster have two cores，and each cluster have there own MTIMER device. The mmio address of mtimecmp for each hart may like

Hi All, Apologies for cross posting multiple lists. Just wanted to reach out to the maximum audience as this is a short notice to set up the first meeting. This is just a quick notice that the first

Hi All, The doodle poll indicates that the 8AM PDT Wednesday is the most preferred slot. This will probably conflict with hypervisor SIG meetings once in a while. We will reschedule that meeting

The implication of that is that either - there is an mmio address that can access different instantiations of mtime/mtimecmp for each requesting hart (depending on the "cluster") - each "cluster"

In the SiFive Core-Local Interruptor (CLINT) device , a core can access the mtimcmp register of all cores in the platform. In the ACLINT spec, If a platform implements multiple MTIMER devices, such

cross-posting for more visibility. ---------- Forwarded message --------- From: Atish Kumar Patra <atishp@...> Date: Thu, Sep 1, 2022 at 11:55 AM Subject: Call for Chair/Vice-Chair Candidates for

Hi All, We are pleased to announce the early formation of Platform Runtime Services(PRS) Task Group with Atish Patra from Rivos as the acting chair and Sunil VL from ventana as the acting vice chair.

Hi All, I received some feedback that they had some conflicts with the proposed time. I adjusted the calendar invite to be for Mon Sept 12th at 8am PT. I will still send out slides prior to that so we

Hi All, I put a meeting on the RISC-V calendar for Thursday September 1 @ 9am PT. I'll send the slides out earlier in the week for people to critique and add suggestions of topics. We'll go over the

Sounds good. As long as we don't annoy anyone with a stream ECR updates to the same table I think that's a fine approach.