Hi All, We'll be having an OS-A SEE Meeting Jan 24 @ 9am PT. Notes are published from previous meetings here. Please read Andrei's proposal and provide feedback. For this meeting I'd like to go over

Hi All, Happy New Year. We'll be having an OS-A SEE Meeting Jan 10 @ 9am PT. See you then! Thanks. -Aaron

Hi All, We were not able to go through the proposal as we didn't have the appropriate people. Please read over the proposal and provide your feedback. -Aaron

Hi All, We'll be meeting this coming Wed Nov 30 @ 9am PT. Link to join: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 We'll be going through Andrei's proposal which can be found

The uint64_t needs two registers on RV32 whereas it only needs one register on RV64. Now if base_addr is the first parameter then for: 1) RV32 a0 = lower 32bits of base address a1 = upper

Hi Anup, Thank you for this proposal, I am happy to see that the legacy console extension is getting a replacement, as I've found it tremendously useful for early debugging in the past. I have a

Hi All, We'll be having an OS-A SEE TG Meeting Nov 15 @ 9am PT. If there are specific topics people are interested in talking about please add them here. Thank you. -Aaron

Hi All, We'll be conducting an OS-A SEE TG meeting Nov 1st @ 9am PT. Link to join is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09

Hi All, We're having a OS-A SEE TG meeting tomorrow Oct 18 at 9am PT. We last met on Oct 4. The meeting slides can be found here. We did not get through everything as we had a discussion about scoping

Thanks Anup - I signed up to that list as well (and thanks for clarifying it's purpose w.r.t. this group).

Hi Andrei, <andrei.warkentin@...> wrote: We now have a separate PRS TG (Platform Runtime Services) for yearly updates to SBI, UEFI, and ACPI specification. Regards, Anup

Dear all, I just wanted to introduce myself and say ‘hi’. I recently joined the Intel SSE group as an engineer focusing on RISC-V standardization (in particular with an interest in

Hi All, This is a reminder that we'll be having the OS-A SEE meeting on October 4th at 9am Pacific Time. The join link is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Also,

The `trig_idx` is intentionally a logical index so that Hypervisors can share the debug triggers between guest and host. As an example, you can look at `counter_idx` defined by SBI PMU extension which

Anup Patel <apatel@...> 于2022年7月14日周四 17:39写道： If I understand correctly, the N here should refer to the logical trigger, not the physical number. sbi needs to maintain

You're right. There is a proposal at https://lists.riscv.org/g/sig-hypervisors/message/151 that will likely be implemented by Syntacore before the end of the year. Tim

To implement hardware breakpoints and watchpoints on the riscv, the trigger in M mode is required. We need an sbi extension for debugging to set the trigger. Please give suggestions and

I declared failure on my part. I'll schedule something early next week (unless people think we can squeeze something in tomorrow or Thurs - appears to be a lot conflicts, though). My apologies for

Hi All, Ved let me know I accidentally had a Google Meet Invite link. The Zoom meeting id is: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Thanks. -Aaron

Hi All, We had our first meeting this past Monday (2022/09/12). I pushed the notes to GitHub. As a reminder each group in RVI has their own folder for stashing collateral. For OS-A SEE TG, the folder