The SBI_DMA_SYNC_NONE if succeeds tells supervisor-mode that target memory regions is valid and DMA sync calls with other directions will go through. In this first draft, I tried to keep various

Could you clarify what SBI_DMA_SYNC_NONE does and how it would help with debugging? Jonathan

What's our policy of bumping up versions? Is there no version 0.3, but just -rc0? I am not sure DSYN is a good name. How about DMAS? Does RVI have plan to introduce cache instructions into the

This patch adds SBI direct memory access synchronize (DSYN)) extension which allows S-mode (or VS-mode) software to explicitly synchronize memory with assistance from the M-mode (or

Hi All, The next platform HSC meeting is scheduled on Fri Jun 4th at 8AM PST. This is a new slot only for this week due to Monday being a holiday in the US for Memorial Day and Wed being the RISC-V

As architected, it setting up breakpoints/watchpoints would have to be handled via SBI. It's possible to trap to M mode and then trampoline back to S as you say. Another option is to have M mode use

That was an interesting read. Do you know what the thinking is on providing self-hosted debug functionality to S-mode? Is this something that's expected to be done via SBI? I think it might be

Chapter 5 of the debug spec covers triggers that are used for self-hosted and/or external debug. The action field of each trigger must be programmed according to table 5.1 to either trap or

Could you link to documentation about self-hosted debug? The only proposed specifications I've seen are for external debug support. Thanks, Jonathan

More properly, this should be a non-normative sentence added to the Machine Timer Registers section in the Priv spec - that notes that setting mtimecmp to the max value effectively disables generation

I would suggest just removing the mtime synchronization code sample, and replacing it with a reminder that clocks have to be synchronized. There's nothing all that subtle about the code so I don't

The mtime synchronization code sample is only for reference. A platform can have it’s own way (hardware/software) of synchronizing MTIME registers. The code sample shows a simple approach to

Hi Neel, You first question is already answered by Greg. Regarding second question/suggestion, I agree we should explicitly state how to disable a pending interrupt. Regards, Anup

From: Abner Chang <abner.chang@...> Signed-off-by: Abner Chang <renba.chang@...> --- contributors.adoc | 1 + 1 file changed, 1 insertion(+) diff --git a/contributors.adoc

From: Abner Chang <abner.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove CLINT

From: Abner Chang <renba.chang@...> Signed-off-by: Abner Chang <renba.chang@...> --- contributors.adoc | 1 + 1 file changed, 1 insertion(+) diff --git a/contributors.adoc

From: Abner Chang <renba.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove

Right, I'm attempting to refer to the effective timer resolution as opposed to the apparent timer unit period. I'm just making explicit what this relaxation implies about capabilities in real systems.

Signed-off-by: Paul Donahue pdonahue@... --- riscv-platform-spec.adoc | 101 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git