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Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

The mtime synchronization code sample is only for reference. A platform can have it’s own way (hardware/software) of synchronizing MTIME registers. The code sample shows a simple approach to

By Anup Patel · #997 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Hi Neel, You first question is already answered by Greg. Regarding second question/suggestion, I agree we should explicitly state how to disable a pending interrupt. Regards, Anup

By Anup Patel · #996 ·

[RESEND PATCH v6 2/2] contributors: Add Abner as contributor

From: Abner Chang <abner.chang@...> Signed-off-by: Abner Chang <renba.chang@...> --- contributors.adoc | 1 + 1 file changed, 1 insertion(+) diff --git a/contributors.adoc

By Abner Chang · #995 ·

[RESEND PATCH v6 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

From: Abner Chang <abner.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove CLINT

By Abner Chang · #994 ·

[PATCH v6 2/2] contributors: Add Abner as contributor

From: Abner Chang <renba.chang@...> Signed-off-by: Abner Chang <renba.chang@...> --- contributors.adoc | 1 + 1 file changed, 1 insertion(+) diff --git a/contributors.adoc

By Abner Chang · #993 ·

[PATCH v6 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

From: Abner Chang <renba.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove

By Abner Chang · #992 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Right, I'm attempting to refer to the effective timer resolution as opposed to the apparent timer unit period. I'm just making explicit what this relaxation implies about capabilities in real systems.

By Josh Scheid · #991 ·

[PATCH v1 2/2] Platform debug requirements

Signed-off-by: Paul Donahue pdonahue@... --- riscv-platform-spec.adoc | 101 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git

By Paul Donahue · #990 ·

[PATCH v1 1/2] Updating changelog

Updating changelog Signed-off-by: Paul Donahue pdonahue@... --- changelog.adoc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/changelog.adoc b/changelog.adoc index 7ec1b1f..cc69971

By Paul Donahue · #989 ·

[PATCH v1 0/2] Updating contributors

Adding myself to list of contributors. Signed-off-by: Paul Donahue pdonahue@... --- contributors.adoc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

By Paul Donahue · #988 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

At least at the platform level, the requirement of a single reference clock for all timers in a "system" (thus preventing first-order drift) may be a desirable requirement. -Josh

By Josh Scheid · #987 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

If you're interested in reading about pure software approaches to clock synchronization, I recommend looking at https://www.usenix.org/conference/nsdi18/presentation/geng. They focus on synchronizing

By Jonathan Behrens <behrensj@...> · #986 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

More recent ARM SBSA requires a 1 GHz counter resolution, but does not place any requirement on the actual measurable 'time" resolution (i.e. a minimum update frequency). So one can have 1 ns

By Greg Favor · #985 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

One other issue with the "mtime" synchronization by SW approach is that this effectively places an upper limit on the achievable timer unit resolution. It'd be some equation based on the ordered

By Josh Scheid · #984 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Note that the "update latency" between a write to "mtime" and a read of the hart-local "time" is unspecified. -Josh

By Josh Scheid · #983 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Architecturally the 'time' CSR reads the same concept of "time" as the 'mtime' register. Simplistically the RDTIME pseudoinstruction reads what is in the 'mtime' register. One implementation is that

By Greg Favor · #982 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Hi, Minor comments: Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this

By Neel Gala · #981 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Hi Josh, I have created a GitHub PR addressing your comments. Please check if you are okay with this. https://github.com/riscv/riscv-aclint/pull/2 Regards, Anup

By Anup Patel · #980 ·

Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Hi Josh, Indeed, I missed adding text regarding verifying delta and ensuring that it is within bounds. Thanks for pointing. I was thinking that aclint_mtime_sync() function should return the

By Anup Patel · #979 ·

Re: [RESEND PATCH v5 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Alistair Francis <Alistair.Francis@...> 於 2021年5月26日週三下午6:57寫道： Alistair, I can understand your concern just like I have to the server extension. The inflexible spec may lead

By Abner Chang · #978 ·

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