Στις 2021-06-03 18:13, Anup Patel έγραψε: Thanks for working on this, it seems simple and clean, some thoughts: a) I also prefer DMAS or something with DMA in the name, and fixed-sized

If CPU is successfully suspended, then the function is implemented by SBI firmware. I don't see why I need to care about the version number. If suspend function is not available, then

Any function not supported, OS can make the SBI call, and check its return value against SBI_ERR_NOT_SUPPORTED. I don't believe an arbitrary version number really helps here. Like you said, SRST

Do we have policies, or planning/schedule of versions? What is the version supposed to be used for? Regards, Bin

Reviewed-by: Bin Meng <bmeng.cn@...>

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The SBI_DMA_SYNC_NONE if succeeds tells supervisor-mode that target memory regions is valid and DMA sync calls with other directions will go through. In this first draft, I tried to keep various

Could you clarify what SBI_DMA_SYNC_NONE does and how it would help with debugging? Jonathan

What's our policy of bumping up versions? Is there no version 0.3, but just -rc0? I am not sure DSYN is a good name. How about DMAS? Does RVI have plan to introduce cache instructions into the

This patch adds SBI direct memory access synchronize (DSYN)) extension which allows S-mode (or VS-mode) software to explicitly synchronize memory with assistance from the M-mode (or

Hi All, The next platform HSC meeting is scheduled on Fri Jun 4th at 8AM PST. This is a new slot only for this week due to Monday being a holiday in the US for Memorial Day and Wed being the RISC-V

As architected, it setting up breakpoints/watchpoints would have to be handled via SBI. It's possible to trap to M mode and then trampoline back to S as you say. Another option is to have M mode use

That was an interesting read. Do you know what the thinking is on providing self-hosted debug functionality to S-mode? Is this something that's expected to be done via SBI? I think it might be

Chapter 5 of the debug spec covers triggers that are used for self-hosted and/or external debug. The action field of each trigger must be programmed according to table 5.1 to either trap or

Could you link to documentation about self-hosted debug? The only proposed specifications I've seen are for external debug support. Thanks, Jonathan

More properly, this should be a non-normative sentence added to the Machine Timer Registers section in the Priv spec - that notes that setting mtimecmp to the max value effectively disables generation

I would suggest just removing the mtime synchronization code sample, and replacing it with a reminder that clocks have to be synchronized. There's nothing all that subtle about the code so I don't