"deprecated" implies is required but will be removed in next version. Use instead: "MBR support is not required." Please, remove this sentence because we do not require to implement this. Best

Kumar Sankaran <ksankaran@...> 於 2021年5月15日 週六 下午1:26寫道： Hi Kunar, I am not able to join at this time slot. Below is my status update, 1. Restructure the spec of PLIC/CLINT/MTIME

Greg Favor <gfavor@...> 於 2021年5月8日 週六 上午1:25寫道： Hi Greg, I am going to restructure the sections for PLIC/CLINT/MTIMER. I am not quite sure your preference of "separate chapters

> +** Platforms are required to provide atleast a 10ns resolution 64-bit counter nit: "at least a" => "an at least" (the former could be misunderstood as saying to have to provide an exactly 10ns

Base spec: - UART - Clock and Timers Server extension: - Clock and Timers Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 44

Adding myself to list of contributors. Signed-off-by: Mayuresh Chitale <mchitale@...> --- contributors.adoc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

This patch describes requirements for the system peripherals like UART, clock and timers for the Linux-2022 platform base spec and the server extension. Changes in V3: Base spec: - Clarified

Sunil V L <sunilvl@...> 於 2021年5月16日 週日 下午9:48寫道： Yes, one of the reasons for having PRM is to reduce the issue of SMI that brings processors to the highest privilege mode

Currently EDK II provides OpenSBI as part of its SEC (Security) code in edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi. When the hypervisor provides the SEC code we will

Am 16. Mai 2021 19:13:47 MESZ schrieb Anup Patel <anup.patel@...>: At least U-Boot relies on OpemSBI for unaligned memory access and may use it for sytem reset. Where will ecalls and exceptions be

Hi, Please note that we should consider that Guest/VM will be directly running in VS-mode (S-mode without hypervisor capabilities) so UEFI firmware will be running entirely in S-mode inside Guest/VM

Hi Rahul, NIT: specifies -> specify

Hi Abner, My understanding is, these features are introduced to reduce some of the issues with SMM mode in x86. I am not sure whether we will have similar issues in risc-v and need to make this

Rahul Pathak <rpathak@...> 於 2021年5月12日 週三 下午5:30寫道： I give my RB for this patch below to keep this work moves on. I would like to have the statement in the Server extension

Hi All, The next platform HSC meeting is scheduled on Monday May 17th 9AM PST. Please note the new time of 9AM PST for this meeting. This change to 9AM PST is only for the May 17th session due to

This patch adds SBI performance monitoring unit (PMU) extension which allows S-mode (or VS-mode) software to configure hardware (or firmware) performance counters with help of M-mode (or HS-mode)

Actually these are different requirements. From the software perspective the counter is required to have atleast 10 ns resolution. But the hardware clock that drives the counter is expected to run at

Hi All, The slides from today's AIA meeting are here: https://docs.google.com/presentation/d/1_wkvY8rtffA_TS0vbUXySH2NKhtLO9ZLvzbIYCjzCE4/edit?usp=sharing Initial ACLINT (or CLINTv2) proposal is

Ping for review