Reviewed-by: Alistair Francis <alistair.francis@...> Alistair

This patch adds SBI v0.2 compliant system reset extension. It defines the sbi_system_reset function which does different things based on reset_type parameter: 1. shutdown - Power-off the entire

Hi Jonathan, I will address your comments in v6 patch. Also I agree, we will have to clearly mention the required reset types for a particular profile (such as server/desktop).

This patch adds SBI performance monitoring unit (PMU) extension which allows S-mode (or VS-mode) software to configure hardware/software performance counters with help of M-mode (or HS-mode)

nit: functionally *the* same as *the* native case... I don't love that all reset types are allowed to fail, but perhaps the thing to do would be to require in the platform spec for server/laptop

I also implemented DTB parsing in Rust as part of RVirt here. I never took the time to spin it out into its own crate though I certainly could if there was interest.

This patch adds SBI v0.2 compliant system reset extension. It defines the sbi_system_reset function which does different things based on reset_type parameter: 1. shutdown - Power-off the entire

<alistair.francis@...> wrote: [ snip ] Thanks -- I hope to push the submodules as public Crates.io entities as soon as they are documented and get decent test coverage. My priority will be the

Hi Al Stone, Unfortunately there is a time conflict between the J.ext meeting and Profiles & Platform meeting on Nov. 2nd. [1] I intend to attend all these meetings. Is it possible to avoid this

Hi Al - Just FYI it's pretty likely I won't be able to attend this meeting on Monday due to another conflict. - Paul On 10/29/20 2:34 PM, Al

Do we need these event types when we already have the cycle and instret CSRs? I think these events should be moved into the cache event type. Ok perhaps this should be something like "delay due to

Sorry, I missed few comments previously.

Hi All, In the next platform spec meeting, we would like to provide a detailed comparison between RISC-V SBI and ARM PSCI. (see attached slides) Hopefully, this will provide a clear picture about

Anup, I'm batting pretty poorly here. Too much context switching between several things this evening. My comments are maybe informative to some others (wrt the event_idx fields), but are irrelevant

Duh, you're right. I forgot about that. You can actually stick with the current spec if you prefer (in which case event_idx.type == 0x0 represents a "no event" type, and event_idx.code should also

Hi Greg, I recall we had discussed this previously, that’s why I used “event_idx.type == 0x1” for HARDWARE general events. Let me update the patch to use your suggestion instead.