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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
Allen Baum
I'm not sure what you're referring to Line 244 list Zihintpause Lines 180-188 list Zvlsseg, Zvamo, Zvediv, Zvqmac, Zve32x, Zve32f, Zve64x, Zve64f, Zve64d Lines 138-147 list Zba, Zbb, Zbc, Zbe, Zbf, Zbm, Zbp, Zbr, Zbs, Zbt (many of which are not yet ratified)
Allen,
There is no 'RVB'... and even the basic options on Zb[abcs] open up 16
possibilities.
Similarly 'V' is a not a single option, but multiple Zv* options.
Finally, Zihintpause is missing.
Cheers,
Philipp.
On Mon, 11 Jul 2022 at 22:16, Allen Baum <allen.baum@...> wrote:
>
> FYI: here is a rough initial draft of the architectural options that I've been able to dig up.
> I know that this is very, very likely to be incomplete.
>
> This is written from the perspective of how to make our reference model model the behavior of a device under test.
> That's a very different use case than what is needed for ACPI, so I have no clue which of these options require a
> parameter to be supplied (as opposed to defining the parameter) and which are don't cares.
>
> Most of this was derived from the Imperas simulator options.
>
> Sail will eventually have CSR definitions that will be supplied from a YAML formatted riscv-config file that describes the properties of a CSR
> (e.g. which are implemented, which bits are RW, what the RO values are, what the ranges of legal values are for RW fields, and what the illegal->legal mapping function is for WARL fields). Entries marked "use CSR definitions" means that don't need to be given names, but can be derived from that YAML description (though the profiles names are restrictions on top of the architecturally allowed behaviors for a particular profile)
>
> The unified discovery spec will be encoding some of these as well, and perhaps some other things which could be derived from this.
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Re: [RISC-V][privileged-software] [RISC-V][tech-os-a-see] [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
Philipp Tomsich <philipp.tomsich@...>
Duplicating the information (i.e. having the individual extensions marked and the profile itself indicated) seems like an error-prone proposal, unless we mandate/enforce consistency checking. Given that this does not provide a significant benefit, it seems safer to stick with the canonical form listing the base and individual extensions.
What is the expected benefit from duplicating this information?
Philipp.
Greg and I did discuss having Unified Discovery (UD) description macros for profiles, e.g. an RV22A bit that indicates support for all of the individual extensions (and option value ranges) required to meet the profile requirements. This was in addition to, not replacement of, all the individual requirements, so you'd still have to set the values for each individual required extension.
The idea of have a macro "bit" (perhaps) for a union of different features, and a way to carve out/remove (and probably replace) some specific extension or option is an interesting one, but sounds fraught with possible weird corner cases.
On Mon, Jul 11, 2022 at 11:28 AM Aaron Durbin < adurbin@...> wrote:
On Mon, Jul 11, 2022 at 12:19 PM Greg Favor < gfavor@...> wrote: On Mon, Jul 11, 2022 at 11:02 AM Aaron Durbin < adurbin@...> wrote: On Fri, Jul 8, 2022 at 3:25 PM Greg Favor < gfavor@...> wrote: To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile about an optional behavior or about a specific parameter value. Any effort to standardize key names and value names across discovery schemes should be kept separate from the acronymic naming in Profiles of specific line items (aka specific key-value pairs).
It's very much the same exercise where the Profile specific options are more narrowly scoped. However, I would imagine the ones created for the Profiles to be a subset of the larger KV space as you named it. If we're going down that road, it would be good to have things consistent.
What I'm saying (or at least my leaning) is that discovery methods should use K-V pairs as they do today (with standardized K names desired). Whereas Profiles have a more limited goal of having extension-like names for specific K-V pairs. The latter names are different animals than the former - not only semantically but also in being short not-so-self-descriptive acronyms (not exactly what you want for K names).
In short, keep these two areas uncoupled from each other and let each struggle down its own path without getting further delayed by each other.
We would then have 2 different namespaces representing many similar constructs. Doesn't that make things more complicated? e.g. If everything that is a non-traditional extension in the Profile has a different way to identify the construct we have 2 different ways of identification.
Somewhat related, will we have a common way to refer to a Profile that identifies itself as a Profile that can be conveyed as a whole to an OS? This discussion is very much analogous to the toolchain discussion which leads to implementations that may not entirely implement a Profile may want set operations for carve outs for non-conformance. But either way, the SW that is being provided this information has to have a way to identify and keep track of these concepts anyway because it needs to deal both with Profiles proper and the exploded components regardless.
If we're going to not call them extensions, I suggest coining something we can use more accurately then. I don't have any great ideas atm.
As Alan mentioned, him and I threw around names like "profentions" (aka profile extensions), although more out of amusement than practical value.
Practically speaking they should have a reasonably self-descriptive (yet short-ish) name. Maybe simply "mandate names"? This also avoids any confusion with extension names and with K and V names that would be used in discovery structures. This also covers mandate items that are one sentence behavioral descriptions (of either a behavioral allowance or disallowance).
Greg
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Re: [RISC-V][tech-os-a-see] [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
Allen Baum
Greg and I did discuss having Unified Discovery (UD) description macros for profiles, e.g. an RV22A bit that indicates support for all of the individual extensions (and option value ranges) required to meet the profile requirements. This was in addition to, not replacement of, all the individual requirements, so you'd still have to set the values for each individual required extension.
The idea of have a macro "bit" (perhaps) for a union of different features, and a way to carve out/remove (and probably replace) some specific extension or option is an interesting one, but sounds fraught with possible weird corner cases.
On Mon, Jul 11, 2022 at 11:28 AM Aaron Durbin < adurbin@...> wrote:
On Mon, Jul 11, 2022 at 12:19 PM Greg Favor < gfavor@...> wrote: On Mon, Jul 11, 2022 at 11:02 AM Aaron Durbin < adurbin@...> wrote: On Fri, Jul 8, 2022 at 3:25 PM Greg Favor < gfavor@...> wrote: To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile about an optional behavior or about a specific parameter value. Any effort to standardize key names and value names across discovery schemes should be kept separate from the acronymic naming in Profiles of specific line items (aka specific key-value pairs).
It's very much the same exercise where the Profile specific options are more narrowly scoped. However, I would imagine the ones created for the Profiles to be a subset of the larger KV space as you named it. If we're going down that road, it would be good to have things consistent.
What I'm saying (or at least my leaning) is that discovery methods should use K-V pairs as they do today (with standardized K names desired). Whereas Profiles have a more limited goal of having extension-like names for specific K-V pairs. The latter names are different animals than the former - not only semantically but also in being short not-so-self-descriptive acronyms (not exactly what you want for K names).
In short, keep these two areas uncoupled from each other and let each struggle down its own path without getting further delayed by each other.
We would then have 2 different namespaces representing many similar constructs. Doesn't that make things more complicated? e.g. If everything that is a non-traditional extension in the Profile has a different way to identify the construct we have 2 different ways of identification.
Somewhat related, will we have a common way to refer to a Profile that identifies itself as a Profile that can be conveyed as a whole to an OS? This discussion is very much analogous to the toolchain discussion which leads to implementations that may not entirely implement a Profile may want set operations for carve outs for non-conformance. But either way, the SW that is being provided this information has to have a way to identify and keep track of these concepts anyway because it needs to deal both with Profiles proper and the exploded components regardless.
If we're going to not call them extensions, I suggest coining something we can use more accurately then. I don't have any great ideas atm.
As Alan mentioned, him and I threw around names like "profentions" (aka profile extensions), although more out of amusement than practical value.
Practically speaking they should have a reasonably self-descriptive (yet short-ish) name. Maybe simply "mandate names"? This also avoids any confusion with extension names and with K and V names that would be used in discovery structures. This also covers mandate items that are one sentence behavioral descriptions (of either a behavioral allowance or disallowance).
Greg
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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
Philipp Tomsich <philipp.tomsich@...>
Allen,
There is no 'RVB'... and even the basic options on Zb[abcs] open up 16
possibilities.
Similarly 'V' is a not a single option, but multiple Zv* options.
Finally, Zihintpause is missing.
Cheers,
Philipp.
toggle quoted message
Show quoted text
On Mon, 11 Jul 2022 at 22:16, Allen Baum <allen.baum@...> wrote:
FYI: here is a rough initial draft of the architectural options that I've been able to dig up.
I know that this is very, very likely to be incomplete.
This is written from the perspective of how to make our reference model model the behavior of a device under test.
That's a very different use case than what is needed for ACPI, so I have no clue which of these options require a
parameter to be supplied (as opposed to defining the parameter) and which are don't cares.
Most of this was derived from the Imperas simulator options.
Sail will eventually have CSR definitions that will be supplied from a YAML formatted riscv-config file that describes the properties of a CSR
(e.g. which are implemented, which bits are RW, what the RO values are, what the ranges of legal values are for RW fields, and what the illegal->legal mapping function is for WARL fields). Entries marked "use CSR definitions" means that don't need to be given names, but can be derived from that YAML description (though the profiles names are restrictions on top of the architecturally allowed behaviors for a particular profile)
The unified discovery spec will be encoding some of these as well, and perhaps some other things which could be derived from this.
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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
Allen Baum
FYI: here is a rough initial draft of the architectural options that I've been able to dig up. I know that this is very, very likely to be incomplete.
This is written from the perspective of how to make our reference model model the behavior of a device under test. That's a very different use case than what is needed for ACPI, so I have no clue which of these options require a parameter to be supplied (as opposed to defining the parameter) and which are don't cares.
Most of this was derived from the Imperas simulator options.
Sail will eventually have CSR definitions that will be supplied from a YAML formatted riscv-config file that describes the properties of a CSR (e.g. which are implemented, which bits are RW, what the RO values are, what the ranges of legal values are for RW fields, and what the illegal->legal mapping function is for WARL fields). Entries marked "use CSR definitions" means that don't need to be given names, but can be derived from that YAML description (though the profiles names are restrictions on top of the architecturally allowed behaviors for a particular profile)
The unified discovery spec will be encoding some of these as well, and perhaps some other things which could be derived from this.
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Re: [RISC-V][tech-os-a-see] [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
On Mon, Jul 11, 2022 at 12:19 PM Greg Favor < gfavor@...> wrote: On Mon, Jul 11, 2022 at 11:02 AM Aaron Durbin < adurbin@...> wrote: On Fri, Jul 8, 2022 at 3:25 PM Greg Favor < gfavor@...> wrote: To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile about an optional behavior or about a specific parameter value. Any effort to standardize key names and value names across discovery schemes should be kept separate from the acronymic naming in Profiles of specific line items (aka specific key-value pairs).
It's very much the same exercise where the Profile specific options are more narrowly scoped. However, I would imagine the ones created for the Profiles to be a subset of the larger KV space as you named it. If we're going down that road, it would be good to have things consistent.
What I'm saying (or at least my leaning) is that discovery methods should use K-V pairs as they do today (with standardized K names desired). Whereas Profiles have a more limited goal of having extension-like names for specific K-V pairs. The latter names are different animals than the former - not only semantically but also in being short not-so-self-descriptive acronyms (not exactly what you want for K names).
In short, keep these two areas uncoupled from each other and let each struggle down its own path without getting further delayed by each other.
We would then have 2 different namespaces representing many similar constructs. Doesn't that make things more complicated? e.g. If everything that is a non-traditional extension in the Profile has a different way to identify the construct we have 2 different ways of identification.
Somewhat related, will we have a common way to refer to a Profile that identifies itself as a Profile that can be conveyed as a whole to an OS? This discussion is very much analogous to the toolchain discussion which leads to implementations that may not entirely implement a Profile may want set operations for carve outs for non-conformance. But either way, the SW that is being provided this information has to have a way to identify and keep track of these concepts anyway because it needs to deal both with Profiles proper and the exploded components regardless.
If we're going to not call them extensions, I suggest coining something we can use more accurately then. I don't have any great ideas atm.
As Alan mentioned, him and I threw around names like "profentions" (aka profile extensions), although more out of amusement than practical value.
Practically speaking they should have a reasonably self-descriptive (yet short-ish) name. Maybe simply "mandate names"? This also avoids any confusion with extension names and with K and V names that would be used in discovery structures. This also covers mandate items that are one sentence behavioral descriptions (of either a behavioral allowance or disallowance).
Greg
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Re: [RISC-V][tech-os-a-see] [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
On Mon, Jul 11, 2022 at 11:02 AM Aaron Durbin < adurbin@...> wrote: On Fri, Jul 8, 2022 at 3:25 PM Greg Favor < gfavor@...> wrote: To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile about an optional behavior or about a specific parameter value. Any effort to standardize key names and value names across discovery schemes should be kept separate from the acronymic naming in Profiles of specific line items (aka specific key-value pairs).
It's very much the same exercise where the Profile specific options are more narrowly scoped. However, I would imagine the ones created for the Profiles to be a subset of the larger KV space as you named it. If we're going down that road, it would be good to have things consistent.
What I'm saying (or at least my leaning) is that discovery methods should use K-V pairs as they do today (with standardized K names desired). Whereas Profiles have a more limited goal of having extension-like names for specific K-V pairs. The latter names are different animals than the former - not only semantically but also in being short not-so-self-descriptive acronyms (not exactly what you want for K names).
In short, keep these two areas uncoupled from each other and let each struggle down its own path without getting further delayed by each other. If we're going to not call them extensions, I suggest coining something we can use more accurately then. I don't have any great ideas atm.
As Alan mentioned, him and I threw around names like "profentions" (aka profile extensions), although more out of amusement than practical value.
Practically speaking they should have a reasonably self-descriptive (yet short-ish) name. Maybe simply "mandate names"? This also avoids any confusion with extension names and with K and V names that would be used in discovery structures. This also covers mandate items that are one sentence behavioral descriptions (of either a behavioral allowance or disallowance).
Greg
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Re: [RISC-V][tech-os-a-see] [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
On Fri, Jul 8, 2022 at 3:25 PM Greg Favor < gfavor@...> wrote: To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile about an optional behavior or about a specific parameter value.
The combinatorics of taking every optional behavior, every parameter that can take on a set of possible values, and every WARL field and the allowed range of possibilities, and then creating an "extension" name for every individual possible "key- value" pair are crazy. (This is why people instead use key-value representations.)
For Profiles, these names have been created on an as-needed basis for specific "key-value" pairs, and no further. Their motivation was to simply have acronymic "extension" names for each of these line items.
In contrast, discovery schemes - like Device Tree, ACPI, and RISC-V Unified Discovery - want something distinctly different. Namely standard "key" names for options, parameters, and WARL fields; standard names for the values of a "key"; and a schema for representing a set of key-value pairs.
Any effort to standardize key names and value names across discovery schemes should be kept separate from the acronymic naming in Profiles of specific line items (aka specific key-value pairs).
It's very much the same exercise where the Profile specific options are more narrowly scoped. However, I would imagine the ones created for the Profiles to be a subset of the larger KV space as you named it. If we're going down that road, it would be good to have things consistent.
Lastly, I think everyone would agree that option / parameter / WARL field names, and their associated value names, are not "extensions". And hence should not be mixed up with the "extension" names created and used in Profiles. Any standardization of "key" names and "value" names should simply focus on usage in discovery schemes (i.e. DT, ACPI, UD). This needs to support all possible key-value pairs.
As to whether all these acronymic line items or "key-value" pairs in Profiles are "extensions", there is probably contention, but I would at least say that these are not extensions in the usual sense. And they should exist and arise solely in the context of Profiles (for the intended purpose of giving an extension-like acronymic name to each line item).
If we're going to not call them extensions, I suggest coining something we can use more accurately then. I don't have any great ideas atm.
In short, I would suggest that it is probably best to keep discussion of these two topics separate.
Greg
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
Allen Baum
Unfortunately, I don't a have single term that would adequately convey the idea. Greg and I were batting around some invented words (e.g. "poption" as a portmanteau of profile-option was my first attempt. It did get better, but that's a low bar) but nothing that you'd find in any dictionary.
On Mon, Jul 11, 2022 at 6:48 AM Aaron Durbin < adurbin@...> wrote:
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
Correct. Do you have a better term that captures such notions? I fully agree that the previous definition of an extension is not the same in this case. FWIW, the profile spec uses both 'extensions' and 'options' within the current proposal for these newly coined names.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: Review request for ACPI ECRs
Stephano Cetola
Slimming down the CC list a bit, as this is off topic for some lists.
Does the Unified DIscovery Specification exit yet? Where can I find it?
I'm in the process of getting status from the new Unified Discovery group:
We're hoping to have a concise draft definition for plummer's conference in sept.
Cheers, Stephano
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Re: [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
I'm also unclear of the "identifier" you mention for other unmentioned option value (e.g. your 64b cache block size example). Who is the consumer of that identifier? Is this a value you would expect to be encoded in the config-struct of on-line discovery? I am building a list of all architectural options that aren't controlled by CSR fields, for what it is worth, as well as all the named option value ranges, regardless of whether they're controlled by a CSR value or not. The intent of this is to be able to configure the Sail model to implement the behavior they control.
Identifier in the sense of a short name/phrase that refers to these ideas. Consumers of that would be both software and day-to-day discussion as it's a succinct identifier that refers to an idea in prose.
Take the Zic64b "extension": it's a shortcut for "Cache blocks must be 64 bytes in size, naturally aligned in the address space." However, there are 3 different cache block operations. So while a Profile name could refer to the whole set of bold options/extensions, there are cases where a system doesn't adhere to a Profile. So how does one convey the cache block size (even if it's 32 bytes for all 3 cache block operations)? I think having a way to identify those architectural options can be very powerful.
FWIW, I completely thought of the the architectural test work you are doing, but I failed to directly mention it in my original email, Allen. Sorry about that.
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
Correct. Do you have a better term that captures such notions? I fully agree that the previous definition of an extension is not the same in this case. FWIW, the profile spec uses both 'extensions' and 'options' within the current proposal for these newly coined names.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
Hi Aaron, On Fri, Jul 08, 2022 at 08:35:40AM -0600, Aaron Durbin wrote: Hi,
I'm top posting with some notes that Furquan helped me put together to
cover the things we've been talking about. We may want to put these and
future notes somewhere else (drive, github, etc) so please let me know what
you think on that front. Also, please add additional thoughts or notes that
were missed. Since the ECRs need to be submitted as word doc, the plan was to archive the notes/comments and ECR versions in the gdrive itself. Please visit https://github.com/riscv-non-isa/riscv-acpi/wiki/ACPI-ASWG-ECR-Process. External people(non-members) can raise issues in github also.
Some high level notes:
- The current proposed ECRs live in the very early (form a boot
standpoint) portion of ACPI. These are needed to easily identify
information for the purposes of booting a kernel. These tables are required
because they can be easily read prior to the ACPI namespace being brought
up. To that end, we should assess the information in each of these early
tables from a "is this required to boot?". Else, we can move to ACPI
namespace proper.
- Are there thoughts on what would live in the ACPI namespace? If there
are already ideas on that, I think we should put those forward.
- We should more thoroughly document in
https://github.com/riscv-non-isa/riscv-acpi what is required and what
field values from the required information is optional/static, etc. It'll
end up being a more thorough spec to direct people to build out the ACPI
data consistently across implementations. I think this is largely an
exercise of going through each data structure and call out fields that are
RISC-V specific.
Will update the guidance doc. - Not entirely unrelated, but what combinations of UEFI, ACPI, and
DeviceTree do we expect? Are we inherently saying UEFI is always present,
and it's an option to utilize ACPI or DeviceTree? This is asked because it
establishes what the dependencies are for gathering certain sets of
information. AIA last bullet point alludes to this in how and what
information is conveyed where. UEFI supports both DT and ACPI. But ACPI is supported only with UEFI (leaving legacy x86 BIOS).
RHCT
- ISA string and extension nodes
- Currently, the organization of RHCT assumes two types of “extensions”
- Boolean based: That can be indicated by presence of ISA string in ISA
string node
- Parameter based: That requires some additional parameters to be passed
in along with the ISA string presence. Example: CBO.
- However, this distinction adds an overhead in terms of ACPI ECRs that
need to pushed out for every extension that is parameter based since it
will require its own table e.g. CMO extension node. This also requires
another system for creating and managing these table names, structures
outside of RVI.
- An alternate approach would be to standardize on the naming/strings
for different extension attributes and utilize that to drive software
enumeration. Example: Zicbom, Zicbop, Zicboz, Zicbo64. Out of these, the
first three are already defined. With the addition of the 4th string that
defines the cache block size, we can eliminate the need for the CMO
extension node.
- However, this requires agreement at the RVI level to converge on the
string naming for these different attributes. Aaron sent out an email to
start that discussion: https://lists.riscv.org/g/tech-os-a-see/message/66
- Our goal should be to reduce the roundtrip in terms of ECRs that are
required for every new extension. If we can create a pointer within ACPI
and maintain rest of the stuff in RVI, then it can help accelerate the
effort.
Not every new extension would need additional parameters to be passed. So far, we have only CBO (as far as I can found) out of all ratified extensions. So, it is less frequent and I think multiple ECRs is not an overhead. Even if we maintain within RVI, I think it may take same/more time and effort to ratify each version of that document.
RINTC
- Divided into two ECRs since IMSIC information (base address and size)
are being added to RINTC to define “interrupt controller”. However, AIA
spec is not yet frozen. So, need to decide whether we should send it as a
single ECR or first send a minimal ECR for RINTC and then follow-up with a
change to add IMSIC details to it once AIA spec is frozen.
- RINTC “IMSIC Size” needs to be explicit that the size includes the
size of S and G level interrupt files. This should be mentioned in prose
instead of reference to guest index bits.
- HartID is being placed in RINTC instead of RHCT because it matches
what ARM and x86 do. No strong opinions about one or the other, but just
keeping it in RINTC for consistency.
- We should evaluate what structures are required pre-ACPI and what can
be processed and handled later as part of ACPI enumeration.
AIA
- Need to decide what the mandatory structures would be to support
variety of combinations:
- IMSIC but no APLIC
- APLIC but no IMSIC
- IMSIC and APLIC
- For the case of IMSIC but no APLIC, the IMSIC structure in AIA ECR is
mostly don't care. The only required field in it is the number of
supervisor/guest mode interrupt identities. If this can be pulled up into
RINTC, then the entire IMSIC structure can be made optional. The fields for
guest/hart/group index are primarily required for the case where IMSIC +
APLIC is supported. This would lead to some duplication at the RINTC level
since all harts would typically have the same number of interrupt files at
supervisor and guest mode, but that might be an okay thing to live with.
As Anup mentioned, we need single MSI controller structure. - Need to elaborate what fast and slow IPI mean in the ECR. This is
primarily to cover the case where IMSIC is being emulated by the hypervisor
and so broadcast IPIs using IMSIC would be slower than SBI. Will update. - Model in IMSIC structure needs more elaboration. The way it is
currently defined requires every vendor to reserve a model ID for their
IMSIC with uefi.org. Can we explore the ideas of using a vendor string
or vendor:device:impl ids for IMSIC that can eliminate the need to make a
roundtrip through uefi.org for the model? We can add manufacturer ID and revision ID combination so that we don't need to send ECRs. Thanks Sunil
-Aaron
On Tue, Jul 5, 2022 at 11:16 AM Sunil V L <sunilvl@...> wrote:
Hi All,
Thanks a lot for great feedback over last week on the ECRs. I have
created version 2 of the ECRs addressing most of the comments. We will be
discussing this version of the ECRs in this week's meeting. Please
provide your comments in this version of the documents.
1) Non-AIA ECRs
a) RHCT - version 2:
https://docs.google.com/document/d/1LlCefO_0GQ_7Tf3lzfMPETEfMlGo2FfLRJ09IMqJKEk/edit?usp=sharing
b)MADT RINTC - version 2:
https://docs.google.com/document/d/1waaAqDyTWvYcCSd1Df-vj0EKCA1nukKF_puclaVYkSo/edit?usp=sharing
2) AIA ECRs
a) MADT - AIA RINTC (version 2) :
https://docs.google.com/document/d/1LBKD1gyi6kOfE3V2WiFOPz1h4MlmxHDj7vkjjfSygBo/edit?usp=sharing
b) MADT - AIA IMSIC/APLIC version 2:
https://docs.google.com/document/d/1zDainvcxD14eawsyc3y1s78zP7ruefyGzcsP1bBak3w/edit?usp=sharing
PoC Code has been updated at same location as earlier.
Thanks
Sunil
On Tue, Jun 21, 2022 at 11:18:02PM +0530, Sunil V L via lists.riscv.org
wrote:
Hi All,
Please review below Engineering Change Request (ECR) to update the ACPI
spec for enabling basic ACPI support for RISC-V.
1) Add INTC structure in MADT Table -
https://docs.google.com/document/d/13YdZzUv0mRHBotdy4Qjqrzb-83mjM31AyEXXfgodcNw/edit?usp=sharing
2) Add new RISC-V Hart Capabilities Table (RHCT).
https://docs.google.com/document/d/1-hQMzSNTEfNqudIENhGxrrb0Yr5MEo4NcZwXZlvdx6k/edit?usp=sharing
3) Add AIA interrupt controllers in MADT table
https://docs.google.com/document/d/1rbdXsON4OMJ0QB3UvkfkIa8hdySbWArIKqPRUli7AU0/edit?usp=sharing
First two ECRs do not have a dependency on any RVI specs which are not
frozen. But the third ECR has a dependency on AIA spec to be frozen.
Hence this AIA ECR will NOT be sent to UEFI forum until AIA spec is
frozen.
The PoC for these ECRs is complete and ACPI enabled Linux boots on qemu
platform. Below are links to the source code for the PoC.
qemu - https://github.com/ventanamicro/qemu/tree/dev-upstream
edk2 - https://github.com/ventanamicro/edk2/tree/dev-upstream
edk2-platforms -
https://github.com/ventanamicro/edk2-platforms/tree/dev-upstream
linux - https://github.com/ventanamicro/linux/tree/dev-upstream
You can find how to build and test these changes in this link -
https://github.com/riscv-non-isa/riscv-acpi/wiki/PoC-:-How-to-build-and-test-ACPI-enabled-kernel
You can provide the feedback by commenting in the document itself. I am
hoping to send at least first two ECRs to UEFI forum by 8th August 2022.
So, appreciate your help to improve these ECRs before 4th August 2022
(45 days from today).
Feel free to reach out if you have any questions.
Thanks!
Sunil
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Re: [RISC-V][tech-os-a-see] [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile about an optional behavior or about a specific parameter value.
The combinatorics of taking every optional behavior, every parameter that can take on a set of possible values, and every WARL field and the allowed range of possibilities, and then creating an "extension" name for every individual possible "key- value" pair are crazy. (This is why people instead use key-value representations.)
For Profiles, these names have been created on an as-needed basis for specific "key-value" pairs, and no further. Their motivation was to simply have acronymic "extension" names for each of these line items.
In contrast, discovery schemes - like Device Tree, ACPI, and RISC-V Unified Discovery - want something distinctly different. Namely standard "key" names for options, parameters, and WARL fields; standard names for the values of a "key"; and a schema for representing a set of key-value pairs.
Any effort to standardize key names and value names across discovery schemes should be kept separate from the acronymic naming in Profiles of specific line items (aka specific key-value pairs).
Lastly, I think everyone would agree that option / parameter / WARL field names, and their associated value names, are not "extensions". And hence should not be mixed up with the "extension" names created and used in Profiles. Any standardization of "key" names and "value" names should simply focus on usage in discovery schemes (i.e. DT, ACPI, UD). This needs to support all possible key-value pairs.
As to whether all these acronymic line items or "key-value" pairs in Profiles are "extensions", there is probably contention, but I would at least say that these are not extensions in the usual sense. And they should exist and arise solely in the context of Profiles (for the intended purpose of giving an extension-like acronymic name to each line item).
In short, I would suggest that it is probably best to keep discussion of these two topics separate.
Greg
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
Allen Baum
I'm also unclear of the "identifier" you mention for other unmentioned option value (e.g. your 64b cache block size example). Who is the consumer of that identifier? Is this a value you would expect to be encoded in the config-struct of on-line discovery? I am building a list of all architectural options that aren't controlled by CSR fields, for what it is worth, as well as all the named option value ranges, regardless of whether they're controlled by a CSR value or not. The intent of this is to be able to configure the Sail model to implement the behavior they control.
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: [RISC-V] [tech-unprivileged] Direction of Identifying Extensions
Allen Baum
If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already exist (which often, but not always, are the legal set of values of a WARL CSR field which must be implemented). So these are constraints on the spec'ed options that are required to run SW on the platform.
On Fri, Jul 8, 2022 at 6:41 AM Aaron Durbin < adurbin@...> wrote: Hi All,
First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene on a single list once it's identified.
The current Profiles ( https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) proposal has coined quite a few new extension names to describe behaviors in the specifications that do not have formal names in the existing specifications. This particular topic came up during our discussion on ACPI bindings for AIA. However, userland, kernel, and firmware specifications are all impacted by this topic so settling on a well understood future direction will reap rewards across the ecosystem.
1. Is this the path we see RISC-V taking for the future? Assigning an identifier to behaviors (and related parameters) within the specifications? 2. If so, where will the official lists of extensions be maintained? Will there be a single source of extension identifiers? Or do people need to look at every potential specification to determine the identifiers? 3. There are some extensions that require parameters besides a binary presence. e.g. Zic64b in the Profile proposal indicates 64 byte cache block sizes for all cache block management, prefetch, and zero operations. That's fine for the Profile, but an implementation that may use different size(s) would need to encode the size in such an identifier. Therefore, I think that we should incorporate these notions more formally when defining identifiers for extension parameters.
I'd love to hear people's thoughts on this topic as it is very important, and I think it could be a good way in formalizing identifiers to all these concepts that can be used throughout the RISC-V ecosystem.
Thank you.
-Aaron
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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
On Fri, Jul 08, 2022 at 08:58:56AM -0700, Mark Himelstein wrote: Just that UD is the source for filling in everything. In my words
foundational and not just orthogonal. I didn't see it below in, for
example, discussions about ISA strings. I wanted to make sure that whether
it be ACPI or DT or something else, they all are created from UD as the
source.
Got it. I understand what you are saying now and agree. regards ved
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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
Anup Patel
Hi Aaron, Few comments below ... On Fri, Jul 8, 2022 at 8:05 PM Aaron Durbin <adurbin@...> wrote:
Hi,
I'm top posting with some notes that Furquan helped me put together to cover the things we've been talking about. We may want to put these and future notes somewhere else (drive, github, etc) so please let me know what you think on that front. Also, please add additional thoughts or notes that were missed.
Some high level notes:
The current proposed ECRs live in the very early (form a boot standpoint) portion of ACPI. These are needed to easily identify information for the purposes of booting a kernel. These tables are required because they can be easily read prior to the ACPI namespace being brought up. To that end, we should assess the information in each of these early tables from a "is this required to boot?". Else, we can move to ACPI namespace proper.
Are there thoughts on what would live in the ACPI namespace? If there are already ideas on that, I think we should put those forward.
We should more thoroughly document in https://github.com/riscv-non-isa/riscv-acpi what is required and what field values from the required information is optional/static, etc. It'll end up being a more thorough spec to direct people to build out the ACPI data consistently across implementations. I think this is largely an exercise of going through each data structure and call out fields that are RISC-V specific.
Not entirely unrelated, but what combinations of UEFI, ACPI, and DeviceTree do we expect? Are we inherently saying UEFI is always present, and it's an option to utilize ACPI or DeviceTree? This is asked because it establishes what the dependencies are for gathering certain sets of information. AIA last bullet point alludes to this in how and what information is conveyed where.
RHCT
ISA string and extension nodes
Currently, the organization of RHCT assumes two types of “extensions”
Boolean based: That can be indicated by presence of ISA string in ISA string node
Parameter based: That requires some additional parameters to be passed in along with the ISA string presence. Example: CBO.
However, this distinction adds an overhead in terms of ACPI ECRs that need to pushed out for every extension that is parameter based since it will require its own table e.g. CMO extension node. This also requires another system for creating and managing these table names, structures outside of RVI.
An alternate approach would be to standardize on the naming/strings for different extension attributes and utilize that to drive software enumeration. Example: Zicbom, Zicbop, Zicboz, Zicbo64. Out of these, the first three are already defined. With the addition of the 4th string that defines the cache block size, we can eliminate the need for the CMO extension node.
However, this requires agreement at the RVI level to converge on the string naming for these different attributes. Aaron sent out an email to start that discussion: https://lists.riscv.org/g/tech-os-a-see/message/66
Our goal should be to reduce the roundtrip in terms of ECRs that are required for every new extension. If we can create a pointer within ACPI and maintain rest of the stuff in RVI, then it can help accelerate the effort.
RINTC
Divided into two ECRs since IMSIC information (base address and size) are being added to RINTC to define “interrupt controller”. However, AIA spec is not yet frozen. So, need to decide whether we should send it as a single ECR or first send a minimal ECR for RINTC and then follow-up with a change to add IMSIC details to it once AIA spec is frozen.
Rather than gating these ACPI ECR efforts on AIA spec being frozen. We should start sending out incremental ECRs for the things that are already ratified. Each ECR will be reviewed separately on the UEFI/ACPI forums which will take its own time. For the next few years, we will certainly see a continuous stream of ECRs being sent-out at regular intervals. RINTC “IMSIC Size” needs to be explicit that the size includes the size of S and G level interrupt files. This should be mentioned in prose instead of reference to guest index bits.
HartID is being placed in RINTC instead of RHCT because it matches what ARM and x86 do. No strong opinions about one or the other, but just keeping it in RINTC for consistency.
We should evaluate what structures are required pre-ACPI and what can be processed and handled later as part of ACPI enumeration.
AIA
Need to decide what the mandatory structures would be to support variety of combinations:
IMSIC but no APLIC
APLIC but no IMSIC
IMSIC and APLIC
For the case of IMSIC but no APLIC, the IMSIC structure in AIA ECR is mostly don't care. The only required field in it is the number of supervisor/guest mode interrupt identities. If this can be pulled up into RINTC, then the entire IMSIC structure can be made optional. The fields for guest/hart/group index are primarily required for the case where IMSIC + APLIC is supported. This would lead to some duplication at the RINTC level since all harts would typically have the same number of interrupt files at supervisor and guest mode, but that might be an okay thing to live with. The IMSIC global structure cannot be made optional because it is used to probe the IMSIC driver. On similar lines, various RINTC structures are used to probe the INTC driver. Also, moving fields from IMSIC global structure to RINTC structure just duplicates information without any simplification for software. Need to elaborate what fast and slow IPI mean in the ECR. This is primarily to cover the case where IMSIC is being emulated by the hypervisor and so broadcast IPIs using IMSIC would be slower than SBI.
Model in IMSIC structure needs more elaboration. The way it is currently defined requires every vendor to reserve a model ID for their IMSIC with uefi.org. Can we explore the ideas of using a vendor string or vendor:device:impl ids for IMSIC that can eliminate the need to make a roundtrip through uefi.org for the model?
-Aaron
On Tue, Jul 5, 2022 at 11:16 AM Sunil V L <sunilvl@...> wrote:
Hi All,
Thanks a lot for great feedback over last week on the ECRs. I have
created version 2 of the ECRs addressing most of the comments. We will be
discussing this version of the ECRs in this week's meeting. Please
provide your comments in this version of the documents.
1) Non-AIA ECRs
a) RHCT - version 2:
https://docs.google.com/document/d/1LlCefO_0GQ_7Tf3lzfMPETEfMlGo2FfLRJ09IMqJKEk/edit?usp=sharing
b)MADT RINTC - version 2:
https://docs.google.com/document/d/1waaAqDyTWvYcCSd1Df-vj0EKCA1nukKF_puclaVYkSo/edit?usp=sharing
2) AIA ECRs
a) MADT - AIA RINTC (version 2) :
https://docs.google.com/document/d/1LBKD1gyi6kOfE3V2WiFOPz1h4MlmxHDj7vkjjfSygBo/edit?usp=sharing
b) MADT - AIA IMSIC/APLIC version 2:
https://docs.google.com/document/d/1zDainvcxD14eawsyc3y1s78zP7ruefyGzcsP1bBak3w/edit?usp=sharing
PoC Code has been updated at same location as earlier.
Thanks
Sunil
On Tue, Jun 21, 2022 at 11:18:02PM +0530, Sunil V L via lists.riscv.org wrote:
Hi All,
Please review below Engineering Change Request (ECR) to update the ACPI
spec for enabling basic ACPI support for RISC-V.
1) Add INTC structure in MADT Table -
https://docs.google.com/document/d/13YdZzUv0mRHBotdy4Qjqrzb-83mjM31AyEXXfgodcNw/edit?usp=sharing
2) Add new RISC-V Hart Capabilities Table (RHCT).
https://docs.google.com/document/d/1-hQMzSNTEfNqudIENhGxrrb0Yr5MEo4NcZwXZlvdx6k/edit?usp=sharing
3) Add AIA interrupt controllers in MADT table
https://docs.google.com/document/d/1rbdXsON4OMJ0QB3UvkfkIa8hdySbWArIKqPRUli7AU0/edit?usp=sharing
First two ECRs do not have a dependency on any RVI specs which are not
frozen. But the third ECR has a dependency on AIA spec to be frozen.
Hence this AIA ECR will NOT be sent to UEFI forum until AIA spec is frozen.
The PoC for these ECRs is complete and ACPI enabled Linux boots on qemu
platform. Below are links to the source code for the PoC.
qemu - https://github.com/ventanamicro/qemu/tree/dev-upstream
edk2 - https://github.com/ventanamicro/edk2/tree/dev-upstream
edk2-platforms - https://github.com/ventanamicro/edk2-platforms/tree/dev-upstream
linux - https://github.com/ventanamicro/linux/tree/dev-upstream
You can find how to build and test these changes in this link -
https://github.com/riscv-non-isa/riscv-acpi/wiki/PoC-:-How-to-build-and-test-ACPI-enabled-kernel
You can provide the feedback by commenting in the document itself. I am
hoping to send at least first two ECRs to UEFI forum by 8th August 2022.
So, appreciate your help to improve these ECRs before 4th August 2022
(45 days from today).
Feel free to reach out if you have any questions.
Thanks!
Sunil
Regards, Anup
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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
On 7/8/22 17:58, mark wrote: Just that UD is the source for filling in everything. In my words foundational and not just orthogonal. I didn't see it below in, for example, discussions about ISA strings. I wanted to make sure that whether it be ACPI or DT or something else, they all are created from UD as the source.
Without wording about this below, readers are left to their own to figure out how to get to the ISA string or DT. I am suggesting that we need a reference in the prose below that says all existence items emanate from UD and that all software uses UD to populate their data structures.
Does this make sense?
Mark Does the Unified DIscovery Specification exit yet? Where can I find it? Best regards Heinrich
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Re: [RISC-V] [tech-aia] [RISC-V][tech-os-a-see] [RISC-V] [tech-unixplatformspec] Review request for ACPI ECRs
mark
Just that UD is the source for filling in everything. In my words foundational and not just orthogonal. I didn't see it below in, for example, discussions about ISA strings. I wanted to make sure that whether it be ACPI or DT or something else, they all are created from UD as the source.
Without wording about this below, readers are left to their own to figure out how to get to the ISA string or DT. I am suggesting that we need a reference in the prose below that says all existence items emanate from UD and that all software uses UD to populate their data structures.
Does this make sense?
Mark
On Fri, Jul 8, 2022 at 8:44 AM Ved Shanbhogue < ved@...> wrote: I think of UD being orthogonal to this discussion.
Firmware world | OS world
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[UD, etc. ]---firmware builds-+->[ACPI/DT]--->OS
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So the comments about early boot etc. in this thread I read as referring
to the OS world. Or was the suggestion that UD be extended to S mode and
we get away with all ACPI/DT enumeration?
regards
ved
On Fri, Jul 08, 2022 at 08:31:23AM -0700, mark wrote:
>agreed. but it all starts with UD.
>
>we had every extension devising their own discovery mechanism and everyone agreed that was not the correct thing to do.
>
>We reduced UD this year to just ASN and extension existence . It should be doable but there is some drag from the past incarnation we are all working through.
>
>Mark
>
>--------
>sent from a mobile device. please forgive any typos.
>
>> On Jul 8, 2022, at 7:48 AM, Philipp Tomsich <philipp.tomsich@...> wrote:
>>
>> Unified DIscovery is expected to be used by firmware to populate DT
>> and ACPI/UEFI tables.
>>
>> Philipp.
>>
>>> On Fri, 8 Jul 2022 at 16:47, Mark Himelstein <markhimelstein@...> wrote:
>>>
>>> just a reminder that we should be moving to unified discovery during boot to feed everything. not isa strings. not csrs.
>>>
>>> --------
>>> sent from a mobile device. please forgive any typos.
>>>
>>> On Jul 8, 2022, at 7:35 AM, Aaron Durbin <adurbin@...> wrote:
>>>
>>>
>>> Hi,
>>>
>>> I'm top posting with some notes that Furquan helped me put together to cover the things we've been talking about. We may want to put these and future notes somewhere else (drive, github, etc) so please let me know what you think on that front. Also, please add additional thoughts or notes that were missed.
>>>
>>> Some high level notes:
>>>
>>> The current proposed ECRs live in the very early (form a boot standpoint) portion of ACPI. These are needed to easily identify information for the purposes of booting a kernel. These tables are required because they can be easily read prior to the ACPI namespace being brought up. To that end, we should assess the information in each of these early tables from a "is this required to boot?". Else, we can move to ACPI namespace proper.
>>> Are there thoughts on what would live in the ACPI namespace? If there are already ideas on that, I think we should put those forward.
>>> We should more thoroughly document in https://github.com/riscv-non-isa/riscv-acpi what is required and what field values from the required information is optional/static, etc. It'll end up being a more thorough spec to direct people to build out the ACPI data consistently across implementations. I think this is largely an exercise of going through each data structure and call out fields that are RISC-V specific.
>>> Not entirely unrelated, but what combinations of UEFI, ACPI, and DeviceTree do we expect? Are we inherently saying UEFI is always present, and it's an option to utilize ACPI or DeviceTree? This is asked because it establishes what the dependencies are for gathering certain sets of information. AIA last bullet point alludes to this in how and what information is conveyed where.
>>>
>>>
>>>
>>> RHCT
>>>
>>> ISA string and extension nodes
>>> Currently, the organization of RHCT assumes two types of “extensions”
>>> Boolean based: That can be indicated by presence of ISA string in ISA string node
>>> Parameter based: That requires some additional parameters to be passed in along with the ISA string presence. Example: CBO.
>>> However, this distinction adds an overhead in terms of ACPI ECRs that need to pushed out for every extension that is parameter based since it will require its own table e.g. CMO extension node. This also requires another system for creating and managing these table names, structures outside of RVI.
>>> An alternate approach would be to standardize on the naming/strings for different extension attributes and utilize that to drive software enumeration. Example: Zicbom, Zicbop, Zicboz, Zicbo64. Out of these, the first three are already defined. With the addition of the 4th string that defines the cache block size, we can eliminate the need for the CMO extension node.
>>> However, this requires agreement at the RVI level to converge on the string naming for these different attributes. Aaron sent out an email to start that discussion: https://lists.riscv.org/g/tech-os-a-see/message/66
>>> Our goal should be to reduce the roundtrip in terms of ECRs that are required for every new extension. If we can create a pointer within ACPI and maintain rest of the stuff in RVI, then it can help accelerate the effort.
>>>
>>> RINTC
>>>
>>> Divided into two ECRs since IMSIC information (base address and size) are being added to RINTC to define “interrupt controller”. However, AIA spec is not yet frozen. So, need to decide whether we should send it as a single ECR or first send a minimal ECR for RINTC and then follow-up with a change to add IMSIC details to it once AIA spec is frozen.
>>> RINTC “IMSIC Size” needs to be explicit that the size includes the size of S and G level interrupt files. This should be mentioned in prose instead of reference to guest index bits.
>>> HartID is being placed in RINTC instead of RHCT because it matches what ARM and x86 do. No strong opinions about one or the other, but just keeping it in RINTC for consistency.
>>> We should evaluate what structures are required pre-ACPI and what can be processed and handled later as part of ACPI enumeration.
>>>
>>> AIA
>>>
>>> Need to decide what the mandatory structures would be to support variety of combinations:
>>>
>>> IMSIC but no APLIC
>>> APLIC but no IMSIC
>>> IMSIC and APLIC
>>>
>>> For the case of IMSIC but no APLIC, the IMSIC structure in AIA ECR is mostly don't care. The only required field in it is the number of supervisor/guest mode interrupt identities. If this can be pulled up into RINTC, then the entire IMSIC structure can be made optional. The fields for guest/hart/group index are primarily required for the case where IMSIC + APLIC is supported. This would lead to some duplication at the RINTC level since all harts would typically have the same number of interrupt files at supervisor and guest mode, but that might be an okay thing to live with.
>>> Need to elaborate what fast and slow IPI mean in the ECR. This is primarily to cover the case where IMSIC is being emulated by the hypervisor and so broadcast IPIs using IMSIC would be slower than SBI.
>>> Model in IMSIC structure needs more elaboration. The way it is currently defined requires every vendor to reserve a model ID for their IMSIC with uefi.org. Can we explore the ideas of using a vendor string or vendor:device:impl ids for IMSIC that can eliminate the need to make a roundtrip through uefi.org for the model?
>>>
>>>
>>> -Aaron
>>>
>>>
>>>> On Tue, Jul 5, 2022 at 11:16 AM Sunil V L <sunilvl@...> wrote:
>>>>
>>>> Hi All,
>>>>
>>>> Thanks a lot for great feedback over last week on the ECRs. I have
>>>> created version 2 of the ECRs addressing most of the comments. We will be
>>>> discussing this version of the ECRs in this week's meeting. Please
>>>> provide your comments in this version of the documents.
>>>>
>>>> 1) Non-AIA ECRs
>>>> a) RHCT - version 2:
>>>> https://docs.google.com/document/d/1LlCefO_0GQ_7Tf3lzfMPETEfMlGo2FfLRJ09IMqJKEk/edit?usp=sharing
>>>> b)MADT RINTC - version 2:
>>>> https://docs.google.com/document/d/1waaAqDyTWvYcCSd1Df-vj0EKCA1nukKF_puclaVYkSo/edit?usp=sharing
>>>> 2) AIA ECRs
>>>> a) MADT - AIA RINTC (version 2) :
>>>> https://docs.google.com/document/d/1LBKD1gyi6kOfE3V2WiFOPz1h4MlmxHDj7vkjjfSygBo/edit?usp=sharing
>>>> b) MADT - AIA IMSIC/APLIC version 2:
>>>> https://docs.google.com/document/d/1zDainvcxD14eawsyc3y1s78zP7ruefyGzcsP1bBak3w/edit?usp=sharing
>>>>
>>>> PoC Code has been updated at same location as earlier.
>>>>
>>>> Thanks
>>>> Sunil
>>>>
>>>> On Tue, Jun 21, 2022 at 11:18:02PM +0530, Sunil V L via lists.riscv.org wrote:
>>>>> Hi All,
>>>>>
>>>>> Please review below Engineering Change Request (ECR) to update the ACPI
>>>>> spec for enabling basic ACPI support for RISC-V.
>>>>>
>>>>> 1) Add INTC structure in MADT Table -
>>>>> https://docs.google.com/document/d/13YdZzUv0mRHBotdy4Qjqrzb-83mjM31AyEXXfgodcNw/edit?usp=sharing
>>>>>
>>>>> 2) Add new RISC-V Hart Capabilities Table (RHCT).
>>>>> https://docs.google.com/document/d/1-hQMzSNTEfNqudIENhGxrrb0Yr5MEo4NcZwXZlvdx6k/edit?usp=sharing
>>>>>
>>>>> 3) Add AIA interrupt controllers in MADT table
>>>>> https://docs.google.com/document/d/1rbdXsON4OMJ0QB3UvkfkIa8hdySbWArIKqPRUli7AU0/edit?usp=sharing
>>>>>
>>>>> First two ECRs do not have a dependency on any RVI specs which are not
>>>>> frozen. But the third ECR has a dependency on AIA spec to be frozen.
>>>>> Hence this AIA ECR will NOT be sent to UEFI forum until AIA spec is frozen.
>>>>>
>>>>> The PoC for these ECRs is complete and ACPI enabled Linux boots on qemu
>>>>> platform. Below are links to the source code for the PoC.
>>>>> qemu - https://github.com/ventanamicro/qemu/tree/dev-upstream
>>>>> edk2 - https://github.com/ventanamicro/edk2/tree/dev-upstream
>>>>> edk2-platforms - https://github.com/ventanamicro/edk2-platforms/tree/dev-upstream
>>>>> linux - https://github.com/ventanamicro/linux/tree/dev-upstream
>>>>>
>>>>> You can find how to build and test these changes in this link -
>>>>> https://github.com/riscv-non-isa/riscv-acpi/wiki/PoC-:-How-to-build-and-test-ACPI-enabled-kernel
>>>>>
>>>>> You can provide the feedback by commenting in the document itself. I am
>>>>> hoping to send at least first two ECRs to UEFI forum by 8th August 2022.
>>>>> So, appreciate your help to improve these ECRs before 4th August 2022
>>>>> (45 days from today).
>>>>>
>>>>> Feel free to reach out if you have any questions.
>>>>>
>>>>> Thanks!
>>>>> Sunil
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>
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