Στις 2021-06-04 23:01, Atish Patra έγραψε:

The firmware code will still be executed while the priv mode is S-mode
right ?
Wouldn't that violate the priv spec ?

M-mode can share a code region with S-mode using PMP/ePMP and let S-mode map that region as executable on its address space. With the current PMP M-mode can define a region as RX for example and both M-mode and S/U-mode will have RX permissions there, with ePMP M-mode can share a code region with S/U-mode that can be RX for M-mode and just X for S/U-mode. I'm obviously talking about small code snippets without any dependencies and references to external symbols etc. A function that flushes the cache for example can be written in such a way.

I'm not very
passionate about this, after all an ecall isn't that expensive and a
DMA
sync is not an operation that happens very frequently, but maybe it's a
good opportunity to talk about this approach.

That's what I am thinking. The only additional cost is just a "ecall
and mret".
IMO, there will be noticeable difference in performance in vDSO-like
interface where S-mode is trying to read something that M-mode
provides. Thus, the base function list are likely candidates [1].
However, the OS makes those SBI calls once during the boot. Thus, it
wouldn't benefit that much.

I was thinking that as part of the extension, we can have an SBI call that would return the address/length of the shared code region (in physical memory) and offsets for each function within that region. The OS will do the SBI call upon registering that SBI extension and will just use the provided function pointers to directly execute code from the shared region. If we are looking for a scenario with a high rate of syncs (lots of packets per second) there will be a noticeable performance difference between a function call and an SBI call, on the other had on such scenarios I'd expect to use the coherent API instead of the non-coherent one.

On Fri, 2021-06-04 at 12:31 +0300, Nick Kossifidis wrote:

Στις 2021-06-03 18:13, Anup Patel έγραψε:

This patch adds SBI direct memory access synchronize (DSYN))
extension
which allows S-mode (or VS-mode) software to explicitly synchronize
memory with assistance from the M-mode (or HS-mode).

Signed-off-by: Anup Patel <anup.patel@...>

Thanks for working on this, it seems simple and clean, some thoughts:

a) I also prefer DMAS or something with DMA in the name, and fixed-
sized
arguments.

Agreed.

b) Device and CPU don't necessarily have the same view of the memory,
we
need to define that physical address is the address the CPU sees.

c) Custom CMOs may only accept virtual addresses instead of physical,
in
which case we'll need to switch them back to virtual in the firmware.
Upon registration SBI may tell the OS if it accepts physical or virtual
addresses and the OS can act accordingly (switch cpu_addr to physical
or
not).

d) Since these operations may also be implemented with custom
instructions (instead of e.g. a register write somewhere) I agree that
keeping the code in the firmware makes more sense than allowing custom
instructions in the kernel, on the other hand these operations are
supposed to be performed on S-mode and doing an ecall for them adds a
bit of an overhead. This extension would be a good candidate for using
the vDSO-like interface we discussed at some point. M-mode could share
a
code region with S-mode (both PMP and ePMP allow this scenario) and
during registration of the extension, SBI will return the physical
address of the region, its size and a set of offsets for the different
functions in there (in this case only one function). 

The firmware code will still be executed while the priv mode is S-mode
right ?

Wouldn't that violate the priv spec ?

I'm not very
passionate about this, after all an ecall isn't that expensive and a
DMA
sync is not an operation that happens very frequently, but maybe it's a
good opportunity to talk about this approach.

That's what I am thinking. The only additional cost is just a "ecall
and mret".

IMO, there will be noticeable difference in performance in vDSO-like
interface where S-mode is trying to read something that M-mode
provides. Thus, the base function list are likely candidates [1].
However, the OS makes those SBI calls once during the boot. Thus, it
wouldn't benefit that much.


[1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#function-listing

Regards,
Nick

--
Regards,
Atish

On Thu, 2021-06-03 at 23:16 +0200, Heinrich Schuchardt wrote:

%s/secion/section/
%s/managment/management/
%s/implemenation/implementation/
%s/requestd/requested/
%s/hierarchial/hierarchical/
%s/inititated/initiated/
%s/recieves/receives/
%s/rententive/retentive/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@...>
---
 riscv-sbi.adoc | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..4b6f2c3 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -31,9 +31,9 @@ https://creativecommons.org/licenses/by/4.0/.

 * Improved document styling and naming conventions
 * Added SBI system reset extension
-* Improved SBI introduction secion
-* Improved documentation of SBI hart state managment extension
-* Added suspend function to SBI hart state managment extension
+* Improved SBI introduction section
+* Improved documentation of SBI hart state management extension
+* Added suspend function to SBI hart state management extension

 === Version 0.2

@@ -52,7 +52,7 @@ of the SBI follows the general RISC-V philosophy of
having a small core along
 with a set of optional modular extensions.

 The higher privilege software providing SBI interface to the
supervisor-mode
-software is referred to as a SBI implemenation or Supervisor Execution
+software is referred to as a SBI implementation or Supervisor
Execution
 Environment (SEE). A SBI implementation (or SEE) can be platform
runtime
 firmware executing in machine-mode (M-mode) (see below <<fig_intro1>>)
or
 it can be some hypervisor executing in hypervisor-mode (HS-mode) (see
below
@@ -741,7 +741,7 @@ along with a unique **HSM state id** for each
state:
                                in the **STOPPED** state.
 | 4        | SUSPENDED       | This hart is in a platform specific
suspend
                                (or low power) state.
-| 5        | SUSPEND_PENDING | The hart has requestd to put itself in
a
+| 5        | SUSPEND_PENDING | The hart has requested to put itself in
a
                                platform specific low power state from
the
                                **STARTED** state and the SBI
implementation
                                is still working to get the hart in the
@@ -764,22 +764,22 @@ image::riscv-sbi-hsm.png[]
 A platform can have multiple harts grouped into a hierarchical
topology
 groups (namely cores, clusters, nodes, etc) with separate platform
specific
 low-power states for each hierarchical group. These platform specific
-low-power states of hierarchial topology groups can be represented as
+low-power states of hierarchical topology groups can be represented as
 platform specific suspend states of a hart. A SBI implementation can
 utilize the suspend states of higher topology groups using one of the
 following approaches:

 . *Platform-coordinated:* In this approach, when a hart becomes idle
the
-  supervisor-mode power-managment software will request deepest
suspend
+  supervisor-mode power-management software will request deepest
suspend
   state for the hart and higher topology groups. A SBI implementation
   should choose a suspend state at higher topology group which is:
 .. Not deeper than the specified suspend state
 .. Wake-up latency is not higher than the wake-up latency of the
    specified suspend state
-. *OS-inititated:* In this approach, the supervisor-mode power-
managment
+. *OS-initiated:* In this approach, the supervisor-mode power-
management
   software will directly request a suspend state for higher topology
group
   after the last hart in that group becomes idle. When a hart becomes
idle,
-  the supervisor-mode power-managment software will always select
suspend
+  the supervisor-mode power-management software will always select
suspend
   state for the hart itself but it will select a suspend state for a
higher
   topology group only if the hart is the last running hart in the
group.
   A SBI implementation should:
@@ -815,7 +815,7 @@ below.
 |===

 This call is asynchronous -- more specifically, the `sbi_hart_start()`
may
-return before target hart starts executing as long as the SBI
implemenation
+return before target hart starts executing as long as the SBI
implementation
 is capable of ensuring the return code is accurate. It is recommended
that
 if the SBI implementation is a platform runtime firmware executing in
 machine-mode (M-mode) then it MUST configure PMP and other M-mode
state
@@ -915,13 +915,13 @@ struct sbiret sbi_hart_suspend(uint32_t
suspend_type,
                                unsigned long opaque)
 ----

-Request the SBI implementation to put the calling hart in a platform
specfic
+Request the SBI implementation to put the calling hart in a platform
specific
 suspend (or low power) state specified by the `suspend_type`
parameter. The
 hart will automatically come out of suspended state and resume normal
-execution when it recieves an interrupt or platform specific hardware
event.
+execution when it receives an interrupt or platform specific hardware
event.

 The platform specific suspend states for a hart can be either
retentive
-or non-rententive in nature. A retentive suspend state will preserve
hart
+or non-retentive in nature. A retentive suspend state will preserve
hart
 register and CSR values for all privilege modes whereas a non-
retentive
 suspend state will not preserve hart register and CSR values.

--
2.30.2

Reviewed-by: Atish Patra <atish.patra@...>
--
Regards,
Atish

On Fri, 2021-06-04 at 21:00 +0800, Bin Meng wrote:

%s/a SBI/an SBI/
%s/A SBI/An SBI/

Signed-off-by: Bin Meng <bmeng.cn@...>
---

 riscv-sbi.adoc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..b02332e 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -52,8 +52,8 @@ of the SBI follows the general RISC-V philosophy of
having a small core along
 with a set of optional modular extensions.
 
 The higher privilege software providing SBI interface to the
supervisor-mode
-software is referred to as a SBI implemenation or Supervisor Execution
-Environment (SEE). A SBI implementation (or SEE) can be platform
runtime
+software is referred to as an SBI implemenation or Supervisor
Execution
+Environment (SEE). An SBI implementation (or SEE) can be platform
runtime
 firmware executing in machine-mode (M-mode) (see below <<fig_intro1>>)
or
 it can be some hypervisor executing in hypervisor-mode (HS-mode) (see
below
 <<fig_intro2>>).
@@ -124,7 +124,7 @@ the specification simple and easily adaptable for
all RISC-V ISA types (i.e.
 RV32, RV64 and RV128). In case the data is defined as 32bit wide,
higher
 privilege software must ensure that it only uses 32 bit data only.
 
-If a SBI function needs to pass a list of harts to the higher
privilege mode,
+If an SBI function needs to pass a list of harts to the higher
privilege mode,
 it must use a hart mask as defined below. This is applicable to any
extensions
 defined in or after v0.2.
 
@@ -765,13 +765,13 @@ A platform can have multiple harts grouped into a
hierarchical topology
 groups (namely cores, clusters, nodes, etc) with separate platform
specific
 low-power states for each hierarchical group. These platform specific
 low-power states of hierarchial topology groups can be represented as
-platform specific suspend states of a hart. A SBI implementation can
+platform specific suspend states of a hart. An SBI implementation can
 utilize the suspend states of higher topology groups using one of the
 following approaches:
 
 . *Platform-coordinated:* In this approach, when a hart becomes idle
the
   supervisor-mode power-managment software will request deepest
suspend
-  state for the hart and higher topology groups. A SBI implementation
+  state for the hart and higher topology groups. An SBI implementation
   should choose a suspend state at higher topology group which is:
 .. Not deeper than the specified suspend state
 .. Wake-up latency is not higher than the wake-up latency of the
@@ -782,7 +782,7 @@ following approaches:
   the supervisor-mode power-managment software will always select
suspend
   state for the hart itself but it will select a suspend state for a
higher
   topology group only if the hart is the last running hart in the
group.
-  A SBI implementation should:
+  An SBI implementation should:
 .. Never choose a suspend state for higher topology group different
from
    the specified suspend state
 .. Always prefer most recent suspend state requested for higher
topology

Reviewed-by: Atish Patra <atish.patra@...>

--
Regards,
Atish

On Sat, 2021-05-29 at 22:42 +0800, Abner Chang wrote:

From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

On v6 commit,
  Remove the changes in Embedded-2022 section.

On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.
- Remove Machine mode timer from previous patch because that is in
the scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer to
ACLINT for the definition of registers

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
mention
  IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not
mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure if
this
  overlaps with your text or not (The timer setion). I can remove
this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..c0ee75d 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,24 @@ include::profiles.adoc[]
 * Start Address
 
 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities
to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local
interrupt
+sources supported by PLIC and how does each of them connect to the
hart
+context is PLIC core implementation-specific. +
+(Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
 PLIC Specification]

IIRC, PLIC spec was never reviewed widely. As this group is more active
now, tt would be good to send it as a separate patch so we can do a
detailed review of that as well.

I am just concerned about semantics rather than technical details.

+for the implementation reference of PLIC operation parameters)
+
+===== ACLINT
+Linux-2020 platform 

We have now official names for the PLATFORM spec. We should refer to
that.

requires the Advanced Core Local Interruptor (ACLINT,
+refer to
+
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V
 ACLINT Specification])
+to provide facilities to route inter-processor interrupt and Machine
mode timer
+interrupt to each RISC-V processor hart.
+

+===== Interrupt Assignments
 
 ==== System Peripherals
 * UART/Serial Console
@@ -289,8 +304,8 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022
 specification.
 
 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>,
+a spec compliant
 
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.
 

--
Regards,
Atish

On Fri, 2021-06-04 at 20:48 +0800, Bin Meng wrote:

Hi Heinrich,

On Fri, Jun 4, 2021 at 8:13 PM Heinrich Schuchardt <
xypron.glpk@...> wrote:

a
On 6/4/21 11:57 AM, Bin Meng wrote:

Signed-off-by: Bin Meng <bmeng.cn@...>
---

  riscv-sbi.adoc | 6 ++++++
  1 file changed, 6 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..8696f97 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -34,6 +34,7 @@ https://creativecommons.org/licenses/by/4.0/.
  * Improved SBI introduction secion
  * Improved documentation of SBI hart state managment extension
  * Added suspend function to SBI hart state managment extension
+* Clarified that a SBI extension cannot be partially implemented

  === Version 0.2

@@ -51,6 +52,11 @@ abstraction for platform (or hypervisor)
specific functionality. The design
  of the SBI follows the general RISC-V philosophy of having a
small core along
  with a set of optional modular extensions.

+SBI extensions as whole are optional but if a SBI <abc>
extension compliant

%s/a SBI/an SBI/ (as you will pronounce SBI as as-bee-aye)

Sure. Will send a new patch to fix other places in the same file.

+with SBI v0.X spec is implemented then all functions of SBI
<abc> extension
+as defined in SBI v0.X are assumed to be present. Basically, a
SBI extension

Can we do away with all the placeholders?

How about:

"SBI extensions as whole are optional but they shall not be
partially
implemented: If sbi_probe_extension() signals that an extension is
available, it must be implemented in total and conform to the SBI
version reported by sbi_get_spec_version()."

This one is more verbose but sounds better to me. May be we should just
explicitly say that "all functions belonging to that extension must be
implemented" similar to the below version.

How about:

If sbi_probe_extension() signals that an extension is available, all
functions that conform to the SBI version reported by
sbi_get_spec_version() must be implemented.

Regards,
Bin

--
Regards,
Atish

%s/a SBI/an SBI/
%s/A SBI/An SBI/

Signed-off-by: Bin Meng <bmeng.cn@...>
---

riscv-sbi.adoc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..b02332e 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -52,8 +52,8 @@ of the SBI follows the general RISC-V philosophy of having a small core along
with a set of optional modular extensions.

The higher privilege software providing SBI interface to the supervisor-mode
-software is referred to as a SBI implemenation or Supervisor Execution
-Environment (SEE). A SBI implementation (or SEE) can be platform runtime
+software is referred to as an SBI implemenation or Supervisor Execution
+Environment (SEE). An SBI implementation (or SEE) can be platform runtime
firmware executing in machine-mode (M-mode) (see below <<fig_intro1>>) or
it can be some hypervisor executing in hypervisor-mode (HS-mode) (see below
<<fig_intro2>>).
@@ -124,7 +124,7 @@ the specification simple and easily adaptable for all RISC-V ISA types (i.e.
RV32, RV64 and RV128). In case the data is defined as 32bit wide, higher
privilege software must ensure that it only uses 32 bit data only.

-If a SBI function needs to pass a list of harts to the higher privilege mode,
+If an SBI function needs to pass a list of harts to the higher privilege mode,
it must use a hart mask as defined below. This is applicable to any extensions
defined in or after v0.2.

@@ -765,13 +765,13 @@ A platform can have multiple harts grouped into a hierarchical topology
groups (namely cores, clusters, nodes, etc) with separate platform specific
low-power states for each hierarchical group. These platform specific
low-power states of hierarchial topology groups can be represented as
-platform specific suspend states of a hart. A SBI implementation can
+platform specific suspend states of a hart. An SBI implementation can
utilize the suspend states of higher topology groups using one of the
following approaches:

. *Platform-coordinated:* In this approach, when a hart becomes idle the
supervisor-mode power-managment software will request deepest suspend
- state for the hart and higher topology groups. A SBI implementation
+ state for the hart and higher topology groups. An SBI implementation
should choose a suspend state at higher topology group which is:
.. Not deeper than the specified suspend state
.. Wake-up latency is not higher than the wake-up latency of the
@@ -782,7 +782,7 @@ following approaches:
the supervisor-mode power-managment software will always select suspend
state for the hart itself but it will select a suspend state for a higher
topology group only if the hart is the last running hart in the group.
- A SBI implementation should:
+ An SBI implementation should:
.. Never choose a suspend state for higher topology group different from
the specified suspend state
.. Always prefer most recent suspend state requested for higher topology
--
2.25.1

Hi Heinrich,

On Fri, Jun 4, 2021 at 8:13 PM Heinrich Schuchardt <xypron.glpk@...> wrote:

a
On 6/4/21 11:57 AM, Bin Meng wrote:

Signed-off-by: Bin Meng <bmeng.cn@...>
---

riscv-sbi.adoc | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..8696f97 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -34,6 +34,7 @@ https://creativecommons.org/licenses/by/4.0/.
* Improved SBI introduction secion
* Improved documentation of SBI hart state managment extension
* Added suspend function to SBI hart state managment extension
+* Clarified that a SBI extension cannot be partially implemented

=== Version 0.2

@@ -51,6 +52,11 @@ abstraction for platform (or hypervisor) specific functionality. The design
of the SBI follows the general RISC-V philosophy of having a small core along
with a set of optional modular extensions.

+SBI extensions as whole are optional but if a SBI <abc> extension compliant

%s/a SBI/an SBI/ (as you will pronounce SBI as as-bee-aye)

Sure. Will send a new patch to fix other places in the same file.

+with SBI v0.X spec is implemented then all functions of SBI <abc> extension
+as defined in SBI v0.X are assumed to be present. Basically, a SBI extension

Can we do away with all the placeholders?

How about:

"SBI extensions as whole are optional but they shall not be partially
implemented: If sbi_probe_extension() signals that an extension is
available, it must be implemented in total and conform to the SBI
version reported by sbi_get_spec_version()."

How about:

If sbi_probe_extension() signals that an extension is available, all
functions that conform to the SBI version reported by
sbi_get_spec_version() must be implemented.

Regards,
Bin

a
On 6/4/21 11:57 AM, Bin Meng wrote:

Signed-off-by: Bin Meng <bmeng.cn@...>
---

riscv-sbi.adoc | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..8696f97 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -34,6 +34,7 @@ https://creativecommons.org/licenses/by/4.0/.
* Improved SBI introduction secion
* Improved documentation of SBI hart state managment extension
* Added suspend function to SBI hart state managment extension
+* Clarified that a SBI extension cannot be partially implemented

=== Version 0.2

@@ -51,6 +52,11 @@ abstraction for platform (or hypervisor) specific functionality. The design
of the SBI follows the general RISC-V philosophy of having a small core along
with a set of optional modular extensions.

+SBI extensions as whole are optional but if a SBI <abc> extension compliant

%s/a SBI/an SBI/ (as you will pronounce SBI as as-bee-aye)

+with SBI v0.X spec is implemented then all functions of SBI <abc> extension
+as defined in SBI v0.X are assumed to be present. Basically, a SBI extension

Can we do away with all the placeholders?

How about:

"SBI extensions as whole are optional but they shall not be partially
implemented: If sbi_probe_extension() signals that an extension is
available, it must be implemented in total and conform to the SBI
version reported by sbi_get_spec_version()."

Best regards

Heinrich

+cannot be partially implemented.
+
The higher privilege software providing SBI interface to the supervisor-mode
software is referred to as a SBI implemenation or Supervisor Execution
Environment (SEE). A SBI implementation (or SEE) can be platform runtime

Signed-off-by: Bin Meng <bmeng.cn@...>
---

riscv-sbi.adoc | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc
index 11c30c3..8696f97 100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -34,6 +34,7 @@ https://creativecommons.org/licenses/by/4.0/.
* Improved SBI introduction secion
* Improved documentation of SBI hart state managment extension
* Added suspend function to SBI hart state managment extension
+* Clarified that a SBI extension cannot be partially implemented

=== Version 0.2

@@ -51,6 +52,11 @@ abstraction for platform (or hypervisor) specific functionality. The design
of the SBI follows the general RISC-V philosophy of having a small core along
with a set of optional modular extensions.

+SBI extensions as whole are optional but if a SBI <abc> extension compliant
+with SBI v0.X spec is implemented then all functions of SBI <abc> extension
+as defined in SBI v0.X are assumed to be present. Basically, a SBI extension
+cannot be partially implemented.
+
The higher privilege software providing SBI interface to the supervisor-mode
software is referred to as a SBI implemenation or Supervisor Execution
Environment (SEE). A SBI implementation (or SEE) can be platform runtime
--
2.25.1

On Fri, Jun 4, 2021 at 5:33 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: Bin Meng <bmeng.cn@...>
Sent: 04 June 2021 14:50
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct memory
access synchronize extension

On Fri, Jun 4, 2021 at 5:06 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: Bin Meng <bmeng.cn@...>
Sent: 04 June 2021 14:12
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct
memory access synchronize extension

On Fri, Jun 4, 2021 at 4:26 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: Bin Meng <bmeng.cn@...>
Sent: 04 June 2021 13:07
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct
memory access synchronize extension

On Thu, Jun 3, 2021 at 11:47 PM Anup Patel <Anup.Patel@...>

wrote:

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Bin Meng
Sent: 03 June 2021 21:02
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add
direct memory access synchronize extension

On Thu, Jun 3, 2021 at 11:13 PM Anup Patel
<anup.patel@...>

wrote:

This patch adds SBI direct memory access synchronize
(DSYN)) extension which allows S-mode (or VS-mode)
software to explicitly synchronize memory with assistance
from the M-mode (or

HS-mode).

Signed-off-by: Anup Patel <anup.patel@...>
---
riscv-sbi.adoc | 95
++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc index
79d98a6..0eb2898
100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -27,6 +27,10 @@

https://creativecommons.org/licenses/by/4.0/.

[preface]
== Change Log

+=== Version 0.4-rc0

What's our policy of bumping up versions?

This extension is meant for SBI v0.4 based on discussion with Atish.

We will be soon freezing SBI v0.3.

Do we have policies, or planning/schedule of versions?

We have not documented a detailed policy/plan/schedule for all SBI
spec versions.

What is the version supposed to be used for?

The set of functions (or definition of functions) provided by a
SBI extension can change over time so the SBI spec version helps
us differentiate this changes.

For example, SBI HSM extension defined in SBI v0.2 does not
include SBI HSM suspend call but the v0.3 does include SBI HSM
suspend call so the Linux CPUIDLE driver will check both SBI spec
version and availability of SBI HSM extension before using SBI HSM

suspend call.

Any function not supported, OS can make the SBI call, and check its
return value against SBI_ERR_NOT_SUPPORTED. I don't believe an
arbitrary version number really helps here.

We can't blindly call a SBI function just to check if it is present or not.

For example, the SBI HSM suspend call will suspend the current CPU and
the CPU will not resume until some interrupt/resume event happens.

If CPU is successfully suspended, then the function is implemented by SBI
firmware. I don't see why I need to care about the version number.
If suspend function is not available, then SBI_ERR_NOT_SUPPORTED is
returned.

That's why we need to use combination of SBI spec version and SBI
probe extension to know whether a particular SBI function is available
or not.

I would like to re-iterate that SBI extensions as whole are optional
but if a SBI <abc> extension compliant with SBI v0.X spec is
implemented then all functions of SBI <abc> extension as defined in
SBI v0.X are assumed to be present. Basically, a SBI extension cannot
be partially implemented.

Is this clearly documented?

Argh, this should have been documented in the introduction chapter.

I can send a patch.

Also, newly defined SBI extensions won't be available on firmware
implementing older SBI spec version so S-mode software should
always probe SBI extensions based on SBI spec version.

For example, SBI SRST extension will be available in only in
firmware implementing SBI v0.3 or higher.

Like you said, SRST extension can be probed. The version number is
not needed.

Checking both SBI spec version before doing SBI probe helps us avoid
unnecessary SBI probe.

Then why did we invent the probe function in the first place? We can rely on
SBI version anyway and maintain a big function matrix in the OS, but as we
introduce more and more extensions over time, I don't think that's scalable.
Checking SBI spec version before doing SBI probe does not help much
compared to a simple probe without caring about version number.

SBI spec = calling convention + a set of SBI extension

SBI extension = a set of SBI functions

We have the SBI extension probing in SBI spec so that SBI implementation
can skip SBI extension for which some other HW mechanism is available.

For example, SBI TIMER extension is not required when underlying HW
has RISC-V Sstc extension proposed by Greg

I know probe() can be helpful. I just don't see the value of using
version number to determine whether a certain SBI extension is
avaiable.

Regards,
Bin

Στις 2021-06-03 18:13, Anup Patel έγραψε:

This patch adds SBI direct memory access synchronize (DSYN)) extension
which allows S-mode (or VS-mode) software to explicitly synchronize
memory with assistance from the M-mode (or HS-mode).
Signed-off-by: Anup Patel <anup.patel@...>

Thanks for working on this, it seems simple and clean, some thoughts:

a) I also prefer DMAS or something with DMA in the name, and fixed-sized arguments.

b) Device and CPU don't necessarily have the same view of the memory, we need to define that physical address is the address the CPU sees.

c) Custom CMOs may only accept virtual addresses instead of physical, in which case we'll need to switch them back to virtual in the firmware. Upon registration SBI may tell the OS if it accepts physical or virtual addresses and the OS can act accordingly (switch cpu_addr to physical or not).

d) Since these operations may also be implemented with custom instructions (instead of e.g. a register write somewhere) I agree that keeping the code in the firmware makes more sense than allowing custom instructions in the kernel, on the other hand these operations are supposed to be performed on S-mode and doing an ecall for them adds a bit of an overhead. This extension would be a good candidate for using the vDSO-like interface we discussed at some point. M-mode could share a code region with S-mode (both PMP and ePMP allow this scenario) and during registration of the extension, SBI will return the physical address of the region, its size and a set of offsets for the different functions in there (in this case only one function). I'm not very passionate about this, after all an ecall isn't that expensive and a DMA sync is not an operation that happens very frequently, but maybe it's a good opportunity to talk about this approach.

Regards,
Nick

On Fri, Jun 4, 2021 at 5:06 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: Bin Meng <bmeng.cn@...>
Sent: 04 June 2021 14:12
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct memory
access synchronize extension

On Fri, Jun 4, 2021 at 4:26 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: Bin Meng <bmeng.cn@...>
Sent: 04 June 2021 13:07
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct
memory access synchronize extension

On Thu, Jun 3, 2021 at 11:47 PM Anup Patel <Anup.Patel@...>

wrote:

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Bin Meng
Sent: 03 June 2021 21:02
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct
memory access synchronize extension

On Thu, Jun 3, 2021 at 11:13 PM Anup Patel <anup.patel@...>

wrote:

This patch adds SBI direct memory access synchronize (DSYN))
extension which allows S-mode (or VS-mode) software to
explicitly synchronize memory with assistance from the M-mode (or

HS-mode).

Signed-off-by: Anup Patel <anup.patel@...>
---
riscv-sbi.adoc | 95
++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc index
79d98a6..0eb2898
100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -27,6 +27,10 @@

https://creativecommons.org/licenses/by/4.0/.

[preface]
== Change Log

+=== Version 0.4-rc0

What's our policy of bumping up versions?

This extension is meant for SBI v0.4 based on discussion with Atish.

We will be soon freezing SBI v0.3.

Do we have policies, or planning/schedule of versions?

We have not documented a detailed policy/plan/schedule for all SBI
spec versions.

What is the version supposed to be used for?

The set of functions (or definition of functions) provided by a SBI
extension can change over time so the SBI spec version helps us
differentiate this changes.

For example, SBI HSM extension defined in SBI v0.2 does not include
SBI HSM suspend call but the v0.3 does include SBI HSM suspend call so
the Linux CPUIDLE driver will check both SBI spec version and
availability of SBI HSM extension before using SBI HSM suspend call.

Any function not supported, OS can make the SBI call, and check its return
value against SBI_ERR_NOT_SUPPORTED. I don't believe an arbitrary version
number really helps here.

We can't blindly call a SBI function just to check if it is present or not.

For example, the SBI HSM suspend call will suspend the current CPU
and the CPU will not resume until some interrupt/resume event
happens.

If CPU is successfully suspended, then the function is implemented by
SBI firmware. I don't see why I need to care about the version number.
If suspend function is not available, then SBI_ERR_NOT_SUPPORTED is
returned.

That's why we need to use combination of SBI spec version and
SBI probe extension to know whether a particular SBI function is
available or not.

I would like to re-iterate that SBI extensions as whole are optional
but if a SBI <abc> extension compliant with SBI v0.X spec is implemented
then all functions of SBI <abc> extension as defined in SBI v0.X are
assumed to be present. Basically, a SBI extension cannot be partially
implemented.

Is this clearly documented?

Also, newly defined SBI extensions won't be available on firmware
implementing older SBI spec version so S-mode software should always
probe SBI extensions based on SBI spec version.

For example, SBI SRST extension will be available in only in firmware
implementing SBI v0.3 or higher.

Like you said, SRST extension can be probed. The version number is not
needed.

Checking both SBI spec version before doing SBI probe helps us avoid
unnecessary SBI probe.

Then why did we invent the probe function in the first place? We can
rely on SBI version anyway and maintain a big function matrix in the
OS, but as we introduce more and more extensions over time, I don't
think that's scalable. Checking SBI spec version before doing SBI
probe does not help much compared to a simple probe without caring
about version number.

Regards,
Bin

On Fri, Jun 4, 2021 at 4:26 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: Bin Meng <bmeng.cn@...>
Sent: 04 June 2021 13:07
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct memory
access synchronize extension

On Thu, Jun 3, 2021 at 11:47 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Bin Meng
Sent: 03 June 2021 21:02
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct
memory access synchronize extension

On Thu, Jun 3, 2021 at 11:13 PM Anup Patel <anup.patel@...>

wrote:

This patch adds SBI direct memory access synchronize (DSYN))
extension which allows S-mode (or VS-mode) software to explicitly
synchronize memory with assistance from the M-mode (or HS-mode).

Signed-off-by: Anup Patel <anup.patel@...>
---
riscv-sbi.adoc | 95
++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc index
79d98a6..0eb2898
100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -27,6 +27,10 @@ https://creativecommons.org/licenses/by/4.0/.
[preface]
== Change Log

+=== Version 0.4-rc0

What's our policy of bumping up versions?

This extension is meant for SBI v0.4 based on discussion with Atish.

We will be soon freezing SBI v0.3.

Do we have policies, or planning/schedule of versions?

We have not documented a detailed policy/plan/schedule for all
SBI spec versions.

What is the version supposed to be used for?

The set of functions (or definition of functions) provided by a
SBI extension can change over time so the SBI spec version helps
us differentiate this changes.

For example, SBI HSM extension defined in SBI v0.2 does not include
SBI HSM suspend call but the v0.3 does include SBI HSM suspend call
so the Linux CPUIDLE driver will check both SBI spec version and
availability of SBI HSM extension before using SBI HSM suspend call.

Any function not supported, OS can make the SBI call, and check its
return value against SBI_ERR_NOT_SUPPORTED. I don't believe an
arbitrary version number really helps here.

Also, newly defined SBI extensions won't be available on firmware
implementing older SBI spec version so S-mode software should
always probe SBI extensions based on SBI spec version.

For example, SBI SRST extension will be available in only in
firmware implementing SBI v0.3 or higher.

Like you said, SRST extension can be probed. The version number is not needed.

Regards,
Bin

On Thu, Jun 3, 2021 at 11:47 PM Anup Patel <Anup.Patel@...> wrote:

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Bin Meng
Sent: 03 June 2021 21:02
To: Anup Patel <Anup.Patel@...>
Cc: tech-unixplatformspec@...; Atish Patra
<Atish.Patra@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] Add direct memory
access synchronize extension

On Thu, Jun 3, 2021 at 11:13 PM Anup Patel <anup.patel@...> wrote:

This patch adds SBI direct memory access synchronize (DSYN)) extension
which allows S-mode (or VS-mode) software to explicitly synchronize
memory with assistance from the M-mode (or HS-mode).

Signed-off-by: Anup Patel <anup.patel@...>
---
riscv-sbi.adoc | 95
++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)

diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc index 79d98a6..0eb2898
100644
--- a/riscv-sbi.adoc
+++ b/riscv-sbi.adoc
@@ -27,6 +27,10 @@ https://creativecommons.org/licenses/by/4.0/.
[preface]
== Change Log

+=== Version 0.4-rc0

What's our policy of bumping up versions?

This extension is meant for SBI v0.4 based on discussion with Atish.

We will be soon freezing SBI v0.3.

Do we have policies, or planning/schedule of versions?

What is the version supposed to be used for?

Regards,
Bin

On Fri, Jun 4, 2021 at 5:17 AM Heinrich Schuchardt <xypron.glpk@...> wrote:

%s/secion/section/
%s/managment/management/
%s/implemenation/implementation/
%s/requestd/requested/
%s/hierarchial/hierarchical/
%s/inititated/initiated/
%s/recieves/receives/
%s/rententive/retentive/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@...>
---
riscv-sbi.adoc | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)

Reviewed-by: Bin Meng <bmeng.cn@...>