Date   

Re: [RESEND PATCH v5 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Alistair Francis
 

On Wed, 2021-05-26 at 10:40 +0000, Anup Patel wrote:
Hi Alistair,

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Alistair Francis
Sent: 26 May 2021 15:48
To: renba.chang@...; tech-unixplatformspec@...
Cc: sunilvl@...; mchitale@...
Subject: Re: [RISC-V] [tech-unixplatformspec] [RESEND PATCH v5 1/2]
riscv-
platform-spec: PLIC and CLINT for Linux-2022 platform

On Wed, 2021-05-26 at 12:57 +0800, renba.chang@... wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc
.
- Remove Machine mode timer from previous patch because that is in
the
scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer
to
ACLINT for the definition of registers

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
mention
  IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not
mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure
if
this
  overlaps with your text or not (The timer setion). I can remove
this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System
Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt
Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 52 ++++++++++++++++++------------------
--
--
 1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index
160c74a..db6dce3 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,23 @@ include::profiles.adoc[]
 * Start Address

 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities
to route
+the non-local interrupts to the external interrupt of a hart
context
+with a given privilege mode in a given hart. The number of non-
local
interrupt
+sources supported by PLIC and how does each of them connect to the
hart
+context is PLIC core implementation-specific. +
+(Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[R
ISC-V
 PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== ACLINT
+Linux-2020 platform requires the Advanced Core Local Interruptor
(ACLINT, refer
+to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RI
SC-V
 ACLINT Specification])
+to provide facilities to route inter-processor interrupt and
Machine
mode timer
+interrupt to each RISC-V processor hart.
+
+===== Interrupt Assignments

 ==== System Peripherals
 * UART/Serial Console
@@ -289,9 +303,8 @@ Any RISC-V system that uses at least RV32/64G
can
meet the Embedded-2022
 specification.

 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CL
IC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>, a spec
+compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CL
IC]
 or both a CLIC and and PLIC.

 If using just a PLIC the system must continue to use the original
basic @@ -303,8 +316,8 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller
and
still
 call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
must
be
+==== Machine Mode Timer
+The RISC-V Machine mode timer (controlled via `mtime` and
`mtimecmp`) must be
 implemented. The two registers must be memory mapped as required
by
the RISC-V
 specification.

@@ -314,27 +327,8 @@ adjacent to each other with the `mtime` region
at
the lower address.
 The starting address of this region can be located anywhere in
 memory, including inside other peripherals, as long as the start
address is
 4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single
hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
You have removed the original  example, but not the original
description. If we
aren't supporting the adjancent addresses the paragraph above this
should be
removed.

I still prefer to allow either adjacent registers (as currently
described) OR the new ACLINT, but if everyone else thinks the ACLINT
is the
only way to go then that's fine.
The ACLINT MTIMER register organization is intentionally kept
compatible
with CLINT timer registers so that ACLINT is backward compatible.
Yep that's great for Linux systems. I haven't seen any embedded systems
besides SiFive that use the CLINT though.

For example SweRVolf uses a specific system controller:
https://github.com/chipsalliance/Cores-SweRVolf/#system-controller

and OpenTitan has it's own timer:
https://docs.opentitan.org/hw/ip/rv_timer/doc/

The ESP32 doesn't even include mtime so that's a different problem.


If you want a different register layout then this has to be defined
somewhere. The hardware cost of organizing registers like CLINT
is not much so it's difficult to justify why we want to organize
registers differently.
For devices that define their own timer I agree that arranging them
like the CLINT shouldn't be a problem. For ones that include the
mtime/mtimecmp in an other system controller I'm worried they will
instead just not try and meet the embedded spec.

We have already defined the layout here, so I don't think it requires
any more work. I agree 100% that it's more of a burden for software to
support two possible timer layouts, but if HW vendors don't opt to
follow the spec then we have to support a lot more.

Anyway, I'm not completely against only allowing ACLINT, I just wanted
to put it out there that it might be difficult for some vendors to
meet. We aren't requiring use of the PLIC or CLIC so it seems a little
strange to then mandate the ACLINT.

Alistair


Regards,
Anup


Alistair

----------------------------
+
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RI
SC-V
 ACLINT Specification]
+defines the memory map layout of Machine mode timer registers.

 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM)
start
at




Re: [RESEND PATCH v5 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Anup Patel
 

Hi Alistair,

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Alistair Francis
Sent: 26 May 2021 15:48
To: renba.chang@...; tech-unixplatformspec@...
Cc: sunilvl@...; mchitale@...
Subject: Re: [RISC-V] [tech-unixplatformspec] [RESEND PATCH v5 1/2] riscv-
platform-spec: PLIC and CLINT for Linux-2022 platform

On Wed, 2021-05-26 at 12:57 +0800, renba.chang@... wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.
- Remove Machine mode timer from previous patch because that is in the
scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer to
ACLINT for the definition of registers

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
mention
  IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure if
this
  overlaps with your text or not (The timer setion). I can remove this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 52 ++++++++++++++++++--------------------
--
 1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index
160c74a..db6dce3 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,23 @@ include::profiles.adoc[]
 * Start Address

 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities
to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local
interrupt
+sources supported by PLIC and how does each of them connect to the
hart
+context is PLIC core implementation-specific. +
+(Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[R
ISC-V
 PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== ACLINT
+Linux-2020 platform requires the Advanced Core Local Interruptor
(ACLINT, refer
+to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RI
SC-V
 ACLINT Specification])
+to provide facilities to route inter-processor interrupt and Machine
mode timer
+interrupt to each RISC-V processor hart.
+
+===== Interrupt Assignments

 ==== System Peripherals
 * UART/Serial Console
@@ -289,9 +303,8 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022
 specification.

 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CL
IC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>, a spec
+compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CL
IC]
 or both a CLIC and and PLIC.

 If using just a PLIC the system must continue to use the original
basic @@ -303,8 +316,8 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller and
still
 call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must
be
+==== Machine Mode Timer
+The RISC-V Machine mode timer (controlled via `mtime` and
`mtimecmp`) must be
 implemented. The two registers must be memory mapped as required by
the RISC-V
 specification.

@@ -314,27 +327,8 @@ adjacent to each other with the `mtime` region at
the lower address.
 The starting address of this region can be located anywhere in
 memory, including inside other peripherals, as long as the start
address is
 4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single
hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
You have removed the original example, but not the original description. If we
aren't supporting the adjancent addresses the paragraph above this should be
removed.

I still prefer to allow either adjacent registers (as currently
described) OR the new ACLINT, but if everyone else thinks the ACLINT is the
only way to go then that's fine.
The ACLINT MTIMER register organization is intentionally kept compatible
with CLINT timer registers so that ACLINT is backward compatible.

If you want a different register layout then this has to be defined
somewhere. The hardware cost of organizing registers like CLINT
is not much so it's difficult to justify why we want to organize
registers differently.

Regards,
Anup


Alistair

----------------------------
+
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RI
SC-V
 ACLINT Specification]
+defines the memory map layout of Machine mode timer registers.

 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM) start
at




Re: [RESEND PATCH v5 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Alistair Francis
 

On Wed, 2021-05-26 at 12:57 +0800, renba.chang@... wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.
- Remove Machine mode timer from previous patch because that is in
the scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer to
ACLINT for the definition of registers

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
mention
  IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not
mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure if
this
  overlaps with your text or not (The timer setion). I can remove
this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 52 ++++++++++++++++++--------------------
--
 1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..db6dce3 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,23 @@ include::profiles.adoc[]
 * Start Address
 
 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities
to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local
interrupt
+sources supported by PLIC and how does each of them connect to the
hart
+context is PLIC core implementation-specific. +
+(Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
 PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== ACLINT
+Linux-2020 platform requires the Advanced Core Local Interruptor
(ACLINT, refer
+to
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V
 ACLINT Specification])
+to provide facilities to route inter-processor interrupt and Machine
mode timer
+interrupt to each RISC-V processor hart.
+
+===== Interrupt Assignments
 
 ==== System Peripherals
 * UART/Serial Console
@@ -289,9 +303,8 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022
 specification.
 
 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>, a spec
+compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.
 
 If using just a PLIC the system must continue to use the original
basic
@@ -303,8 +316,8 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller and
still
 call it a PLIC or CLIC.
 
-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
must be
+==== Machine Mode Timer
+The RISC-V Machine mode timer (controlled via `mtime` and
`mtimecmp`) must be
 implemented. The two registers must be memory mapped as required by
the RISC-V
 specification.
 
@@ -314,27 +327,8 @@ adjacent to each other with the `mtime` region
at the lower address.
 The starting address of this region can be located anywhere in
 memory, including inside other peripherals, as long as the start
address is
 4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single
hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
You have removed the original example, but not the original
description. If we aren't supporting the adjancent addresses the
paragraph above this should be removed.

I still prefer to allow either adjacent registers (as currently
described) OR the new ACLINT, but if everyone else thinks the ACLINT is
the only way to go then that's fine.

Alistair

----------------------------
+
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V
 ACLINT Specification]
+defines the memory map layout of Machine mode timer registers.
 
 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM) start
at


RISC-V ACLINT specification is now hosted on RISC-V GitHub

Anup Patel
 

Hi All,

The RISC-V ACLINT specification is now hosted on RISC-V GitHub page:
https://github.com/riscv/riscv-aclint
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc

Please review this at your end send feedback on AIA/Platform mailing
lists.

The RISC-V ACLINT specification is intended to be small and backward
compatible to the SiFive CLINT specification which makes existing
RISC-V platforms compliant with the RISC-V ACLINT specification.

Overall, from platforms specification perspective it complements
the RISC-V AIA specification by providing IPI and Timer functionality.

A complete functional implementation is available for QEMU RISC-V
along with OpenSBI and Linux RISC-V changes. Please refer, the
riscv_aclint_v1 branch in following repos:
https://github.com/avpatel/qemu.git
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git

To enable ACLINT emulation on QEMU, use "-M virt,aclint=on"
instead of just "-M virt" in your QEMU command line. For now,
QEMU supports ACLINT only for virt machine.

Regards,
Anup


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 

Hi Alistar,
Please check if you are ok with v5 patch.
Thanks
Abner

Anup Patel <anup.patel@...> 於 2021年5月25日 週二 下午4:25寫道:

Hi Abner,

 

I agree with your points 1) to 3).

 

Regards,

Anup

 

From: Abner Chang <renba.chang@...>
Sent: 25 May 2021 13:46
To: Anup Patel <Anup.Patel@...>
Cc: Alistair Francis <Alistair.Francis@...>; sunilvl@...; tech-unixplatformspec@...; mchitale@...
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

 

 

Anup Patel <Anup.Patel@...> 2021525 週二 下午12:39寫道:

Hi Alistar,

> -----Original Message-----
> From: tech-unixplatformspec@... <tech-
> unixplatformspec@...> On Behalf Of Alistair Francis
> Sent: 24 May 2021 12:54
> To: renba.chang@...
> Cc: sunilvl@...; tech-unixplatformspec@...;
> mchitale@...
> Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-
> spec: PLIC and CLINT for Linux-2022 platform
>
> On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:
> >
> >
> > Alistair Francis <Alistair.Francis@...> 2021524 週一
> > 上午11:42寫道:
> > > On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> > > > From: Abner Chang <renba.chang@...>
> > > >
> > > > Initial description of PLIC  CLINT section of Linux-2022 platform.
> > > >
> > > > Is this what we want to see of CLINT/Machine mode timer in the
> > > > platform spec?
> > > >
> > > > On v4 commit,
> > > > - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> > > > - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> > > > mention
> > > >   IPI because AIA already supported it.
> > > > - In Embedded-2022 Machine mode timer section, CLINT is not
> > > > mandatory.
> > > > - Separate section in appendix for the Machine mode timer
> > > > registers
> > > >
> > > > On v3 commit,
> > > > - Address review comments.
> > > >
> > > > On v2 commit,
> > > > - CLINT is not deprecated.
> > > >
> > > > - Add a standalone section for Machine Mode Timer in System
> > > > Peripherals.
> > > >   Do you think this is a good place for Machine Mode Timer?
> > > >   @Mayuresh, please check if you are ok with this change, not sure
> > > if
> > > > this
> > > >   overlaps with your text or not (The timer setion). I can remove
> > > > this
> > > >   if you prefer to put this with your patch.
> > > >
> > > > - In Embedded-2022, refer to Machine Mode Timer in System
> > > Peripherals
> > > >   section and CLINT in Linux-2022 Platform.
> > > >   @Alistair, is this ok?
> > > >
> > > > On v1 commit,
> > > > - Not sure where to put the [DEPRECATED].
> > > > - Change the reference of PLIC in section 2.2.2. Interrupt
> > > Controller
> > > > to
> > > >   1.1.3.2 PLIC + CLINT section.
> > > >
> > > > Signed-off-by: Abner Chang <renba.chang@...>
> > > > Cc: Alistair Francis <alistair.francis@...>
> > > > Cc: Sunil V L <sunilvl@...>
> > > > Cc: Mayuresh Chitale <mchitale@...>
> > > > ---
> > > >  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
> > > > --
> > > --
> > > > --
> > > >  1 file changed, 62 insertions(+), 42 deletions(-)
> > > >
> > > > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > > > index 160c74a..f8838ab 100644
> > > > --- a/riscv-platform-spec.adoc
> > > > +++ b/riscv-platform-spec.adoc
> > > > @@ -49,15 +49,37 @@ include::profiles.adoc[]
> > > >  * Start Address
> > > >
> > > >  ==== Interrupt Controller
> > > > -* AIA
> > > > -* PLIC + CLINT
> > > > -* Interrupt Assignments
> > > > +===== AIA[[AIA]]
> > > > +===== PLIC[DEPRECATED][[PLIC]]
> > > > +The Platform Level Interrupt Controller (PLIC) provides
> > > > facilities
> > > > to route
> > > > +the non-local interrupts to the external interrupt of a hart
> > > context
> > > > +with a given privilege mode in a given hart. The number of non-
> > > local
> > > > interrupt
> > > > +sources supported by PLIC and how does each of them connect to
> > > > the
> > > > hart
> > > > +context is PLIC core implementation-specific. + (Refer to
> > > >
> > > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc
> > > [RISC-V
> > > >  PLIC Specification]
> > > > +for the implementation reference of PLIC operation parameters)
> > > > +
> > > > +===== CLINT[[CLINT]]
> > > > +On the contrast to PLIC, the Core Local Interrupt (CLINT)
> > > > provides
> > >
> > > I don't think this is a contrast to the PLIC, it's just a different
> > > functionality.
> > >
> >
> > Can rephase it.
> > >
> > > I'm also not sure the CLINT should be in the interrupt controller
> > > section. It is the Core Local INTerruptor (CLINT), not an interrupt
> > > controller.
> > >
> >
> > Hmm.. CLINT is not a sort of interrupt controller but seems to me it
> > is unnecessary to create another section apart from the Interrupt
> > Controller section.
>
> It probably makes more sense to add a timer section and put the CLNIT there
> instead of forcing it into the interrupt controller section, when it isn't really an
> interrupt controller.
>
> > >
> > > > +facilities to trigger local interrupt of
> > > <<MachineModeTimer,Machine
> > > > mode timer>> to hart.
> > > > +
> > > > +===== Interrupt Assignments
> > > >
> > > >  ==== System Peripherals
> > > > -* UART/Serial Console
> > > > -* Clocks
> > > > -* Timers
> > > > -* Watchdog Timers
> > > > +===== UART/Serial Console
> > > > +===== Clocks
> > > > +===== Timers
> > > > +
> > > > +===== Machine Mode Timer[[MachineModeTimer]] Machine mode
> timer
> > > > +is required for Linux-2022 platform and
> > > > incorporate with
> > > > +<<CLINT,CLINT>> to trigger the timer event to hart. The format
> > > > of
> > > > Machine mode timer operation parameters
> > > > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> > >
> > > s/must compliant/must be compliant/g
> > >
> >
> > will correct this
> > >
> > > > Privilege specification section 3.1.10.
> > > > +The base address of the memory map registers of Machine mode
> > > > timer
> > > > is platform implementation-specific,
> > > > +however the offset of `mtime` and `mtimecmp` registers are fixed
> > > as
> > > > +<<machineModeTimerRegs,Machine mode timer registers>>.
> > > > +
> > > > +
> > > > +===== Watchdog Timers
> > > >
> > > >  ==== Boot Process
> > > >  * Firmware
> > > > @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
> > > can
> > > > meet the Embedded-2022
> > > >  specification.
> > > >
> > > >  ==== Interrupt Controller
> > > > -Embedded systems are recommended to use a spec compliant
> > > > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > > > -
> > > >
> > > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
> > > CLIC]
> > > > +Embedded systems are recommended to use a spec compliant
> > > > <<PLIC,PLIC>>, a spec
> > > > +compliant
> > > >
> > > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
> > > CLIC]
> > > >  or both a CLIC and and PLIC.
> > > >
> > > >  If using just a PLIC the system must continue to use the original
> > > > basic @@ -303,38 +324,9 @@ must be supported.
> > > >  Embedded systems cannot use a non-compliant interrupt controller
> > > and
> > > > still
> > > >  call it a PLIC or CLIC.
> > > >
> > > > -==== Machine Timer
> > > > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > > > must be -implemented. The two registers must be memory mapped as
> > > > required
> > > by
> > > > the RISC-V
> > > > -specification.
> > > > -
> > > > -The Embedded-2022 specification requires that the registers be
> > > > mapped -adjacent to each other with the `mtime` region at the
> > > > lower
> > > address.
> > > > -
> > > > -The starting address of this region can be located anywhere in
> > > > -memory, including inside other peripherals, as long as the start
> > > > address is
> > > > -4 byte aligned.
> > > > -
> > > > -An example of the memory layout for a 32-bit system with a single
> > > > hart is below
> > > > -
> > > > --------------------------
> > > > -=========================
> > > > -| 0x00 |  mtime low     |
> > > > -| 0x04 |  mtime high    |
> > > > -| 0x08 |  mtimecmp low  |
> > > > -| 0x0C |  mtimecmp high |
> > > > -=========================
> > > > --------------------------
> > > > -
> > > > -and for a 64-bit system with 2 harts
> > > > -
> > > > ----------------------------
> > > > -===========================
> > > > -| 0x00 |  mtime           |
> > > > -| 0x08 |  mtimecmp hart 1 |
> > > > -| 0x10 |  mtimecmp hart 2 |
> > > > -===========================
> > > > ----------------------------
> > > > +==== Machine Mode Timer
> > > > +The Embedded-2022 specification requires RISC-V
> > > > <<MachineModeTimer,Machine mode timer>> to be implemented.
> > > > +The Machine mode timer could be incorporated with the Core Local
> > > > Interrupt (<<CLINT, CLINT>>) or the specific event trigger
> > > mechanism
> > >
> > > CLINT is INTerruptor not just Interrupt.
> > >
> >
> > yes, will correct it
> > >
> > > > according to the platform design.
> > >
> > > What specific trigger mechanism?
> > >
> >
> > platform implementation-specific trigger mechanism?  or just remove
>
> I meant you didn't say what the mechanism is. It should be explicit, so that
> there are no ambiguities.
>
> > this? I put this just because the previous feedback says a small
> > system may not have CLINT for the m-mode timer.
>
> I would be in favour of saying either do what we already have written here OR
> a CLINT.
>
> If we go with something else that's ok, we just need to be clear about what it
> is.
>
> > >
> > > >
> > > >  ==== Memory Map
> > > >  It is recommended that main memory and loadable code (not ROM)
> > > start
> > > > at
> > > > @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> > > > include at least 4 regions, although
> > > >  if possible more should be supported to allow more flexibility.
> > > > Hardware
> > > >  implementations should aim for supporting at least 16 PMP
> > > > regions.
> > > >
> > > > +// Appendix sections
> > > > +== Appendix
> > > > +=== Machine Mode Timer Registers [[MachineModeTimerRegs]] The
> > > > +base address of Machine mode timer operation parameters is
> > > > platform implementation-specific. The Machine mode timer compare
> > > > registers (`mtimecmp`) for each hart is located at offset 0 and
> > > > the layout is organized as below table.
> > >
> > > Can we maintain what we have for the embedded spec?
> > >
> >
> > Do you mean to maintain the register layout(offset) originally defined
> > in the 2.2.3. for embedded systems?
>
> Yes. I worry that mandating a CLINT layout is too restrictive and that no one
> will end up following the embedded-2022 spec then. I would be in favour of
> saying CLINT or the memory layout we already have.

The ACLINT spec does not enforce any memory layout.
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc

The ACLINT is backward compatible to CLINT we should refer ACLINT
in-place of CLINT. This gives platform vendors flexibility to choose
their or memory layout and implement only certain parts of ACLINT
as required.

 

Hi Anup and Alistair. 

With ACLINT spec defined, I think we can revise this patch as below,

1.Remove CLINT from platform spec

2 Mention ACLINT in platform spec for Linux2020 platform and have a link to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.

3. Remove Machine mode timer from system peripheral because that is in the scope of ACLINT

4. For Embedded-2022 platform, mention Machine mode timer and refer to ACLINT for the definition of registers.

Any other thoughts?

 

Abner

 


Regards,
Anup

>
> > I think we have the register layout as below to be compliant with the
> > m-mode timer registers defined in SiFive CLINT.
>
> I don't think that's flexible enough and that vendors won't want to follow it as
> they already have other IP they are using for timers.
>
> Alistair
>
> > Or do you mean something else?
> >
> > >  It allows the
> > > memory maps to be inside of a MMIO device. For example they can be
> > > registers inside of a general system controller.
> > >
> > >
> > > Also it looks like the lines are a little long here, can be bring
> > > them back to 80 charecters?
> > >
> >
> > sure.
> > >
> > > > +
> > > > +.Registers layout of mtimecmp
> > > > +[width="60%",cols="1,^3,^3"]
> > > > +|=======
> > > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > > RV32*
> > > > +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > > > +|`0x0004` ||mtimecmp high for hart 0
> > > > +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > > > +|`0x000c` ||mtimecmp high for hart 1
> > > > +|... ||
> > > > +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > > > +|`0x7ff4` ||mtimecmp high for hart 4094
> > > > +|=======
> > > > +
> > > > +The Machine mode timer counter (`mtime`) is located at offset
> > > 0x7ff8
> > > > from the base address of operation parameters.
> > > > +
> > > > +.Registers layout of mtime
> > > > +[width="60%",cols="1,^3,^3"]
> > > > +|=======
> > > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > > RV32*
> > > > +|`0x7ff8` |mtime|mtime low
> > > > +|`0x7ffc` ||mtime high
> > > > +|=======
> > >
> > > Are you saying for a small embedded single core CPU we need to put
> > > mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
> > > addresses between them?
> > >
> > > Alistair
> > >
> > > > +
> > > >  // acknowledge all of the contributors
> > > >  include::contributors.adoc[]
> > >
>
>
>
>
>


[RESEND PATCH v5 2/2] contributors: Add Abner as contributor

Abner Chang
 

From: Abner Chang <renba.chang@...>

Signed-off-by: Abner Chang <renba.chang@...>
---
contributors.adoc | 1 +
1 file changed, 1 insertion(+)

diff --git a/contributors.adoc b/contributors.adoc
index 3d19411..73b99c4 100644
--- a/contributors.adoc
+++ b/contributors.adoc
@@ -27,6 +27,7 @@ Andrew Waterman,
Kumar Sankaran,
Alistair Francis,
Sunil V L.
+Abner Chang

If you have contributed and are not listed, do let us know. We haven't
forgotten you, but we may have forgotten to edit this list.
--
2.19.0.windows.1


[RESEND PATCH v5 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 

From: Abner Chang <renba.chang@...>

Initial description of PLIC CLINT section of Linux-2022 platform.

On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.
- Remove Machine mode timer from previous patch because that is in the scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer to ACLINT for the definition of registers

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't mention
IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System Peripherals.
Do you think this is a good place for Machine Mode Timer?
@Mayuresh, please check if you are ok with this change, not sure if this
overlaps with your text or not (The timer setion). I can remove this
if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
section and CLINT in Linux-2022 Platform.
@Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
riscv-platform-spec.adoc | 52 ++++++++++++++++++----------------------
1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..db6dce3 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,23 @@ include::profiles.adoc[]
* Start Address

==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local interrupt
+sources supported by PLIC and how does each of them connect to the hart
+context is PLIC core implementation-specific. +
+(Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== ACLINT
+Linux-2020 platform requires the Advanced Core Local Interruptor (ACLINT, refer
+to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V ACLINT Specification])
+to provide facilities to route inter-processor interrupt and Machine mode timer
+interrupt to each RISC-V processor hart.
+
+===== Interrupt Assignments

==== System Peripherals
* UART/Serial Console
@@ -289,9 +303,8 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
specification.

==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant <<PLIC,PLIC>>, a spec
+compliant https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
or both a CLIC and and PLIC.

If using just a PLIC the system must continue to use the original basic
@@ -303,8 +316,8 @@ must be supported.
Embedded systems cannot use a non-compliant interrupt controller and still
call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must be
+==== Machine Mode Timer
+The RISC-V Machine mode timer (controlled via `mtime` and `mtimecmp`) must be
implemented. The two registers must be memory mapped as required by the RISC-V
specification.

@@ -314,27 +327,8 @@ adjacent to each other with the `mtime` region at the lower address.
The starting address of this region can be located anywhere in
memory, including inside other peripherals, as long as the start address is
4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single hart is below
-
--------------------------
-=========================
-| 0x00 | mtime low |
-| 0x04 | mtime high |
-| 0x08 | mtimecmp low |
-| 0x0C | mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 | mtime |
-| 0x08 | mtimecmp hart 1 |
-| 0x10 | mtimecmp hart 2 |
-===========================
----------------------------
+https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V ACLINT Specification]
+defines the memory map layout of Machine mode timer registers.

==== Memory Map
It is recommended that main memory and loadable code (not ROM) start at
--
2.19.0.windows.1


[PATCH v5] contributors: Add Abner as contributor

Abner Chang
 

From: Abner Chang <renba.chang@...>

Signed-off-by: Abner Chang <renba.chang@...>
---
contributors.adoc | 1 +
1 file changed, 1 insertion(+)

diff --git a/contributors.adoc b/contributors.adoc
index 3d19411..73b99c4 100644
--- a/contributors.adoc
+++ b/contributors.adoc
@@ -27,6 +27,7 @@ Andrew Waterman,
Kumar Sankaran,
Alistair Francis,
Sunil V L.
+Abner Chang

If you have contributed and are not listed, do let us know. We haven't
forgotten you, but we may have forgotten to edit this list.
--
2.19.0.windows.1


[PATCH v5] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 

From: Abner Chang <renba.chang@...>

Initial description of PLIC CLINT section of Linux-2022 platform.

On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.
- Remove Machine mode timer from previous patch because that is in the scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer to ACLINT for the definition of registers

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't mention
IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System Peripherals.
Do you think this is a good place for Machine Mode Timer?
@Mayuresh, please check if you are ok with this change, not sure if this
overlaps with your text or not (The timer setion). I can remove this
if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
section and CLINT in Linux-2022 Platform.
@Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
riscv-platform-spec.adoc | 52 ++++++++++++++++++----------------------
1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..db6dce3 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,23 @@ include::profiles.adoc[]
* Start Address

==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local interrupt
+sources supported by PLIC and how does each of them connect to the hart
+context is PLIC core implementation-specific. +
+(Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== ACLINT
+Linux-2020 platform requires the Advanced Core Local Interruptor (ACLINT, refer
+to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V ACLINT Specification])
+to provide facilities to route inter-processor interrupt and Machine mode timer
+interrupt to each RISC-V processor hart.
+
+===== Interrupt Assignments

==== System Peripherals
* UART/Serial Console
@@ -289,9 +303,8 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
specification.

==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant <<PLIC,PLIC>>, a spec
+compliant https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
or both a CLIC and and PLIC.

If using just a PLIC the system must continue to use the original basic
@@ -303,8 +316,8 @@ must be supported.
Embedded systems cannot use a non-compliant interrupt controller and still
call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must be
+==== Machine Mode Timer
+The RISC-V Machine mode timer (controlled via `mtime` and `mtimecmp`) must be
implemented. The two registers must be memory mapped as required by the RISC-V
specification.

@@ -314,27 +327,8 @@ adjacent to each other with the `mtime` region at the lower address.
The starting address of this region can be located anywhere in
memory, including inside other peripherals, as long as the start address is
4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single hart is below
-
--------------------------
-=========================
-| 0x00 | mtime low |
-| 0x04 | mtime high |
-| 0x08 | mtimecmp low |
-| 0x0C | mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 | mtime |
-| 0x08 | mtimecmp hart 1 |
-| 0x10 | mtimecmp hart 2 |
-===========================
----------------------------
+https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V ACLINT Specification]
+defines the memory map layout of Machine mode timer registers.

==== Memory Map
It is recommended that main memory and loadable code (not ROM) start at
--
2.19.0.windows.1


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Anup Patel
 

Hi Abner,

 

I agree with your points 1) to 3).

 

Regards,

Anup

 

From: Abner Chang <renba.chang@...>
Sent: 25 May 2021 13:46
To: Anup Patel <Anup.Patel@...>
Cc: Alistair Francis <Alistair.Francis@...>; sunilvl@...; tech-unixplatformspec@...; mchitale@...
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

 

 

Anup Patel <Anup.Patel@...> 2021525 週二 下午12:39寫道:

Hi Alistar,

> -----Original Message-----
> From: tech-unixplatformspec@... <tech-
> unixplatformspec@...> On Behalf Of Alistair Francis
> Sent: 24 May 2021 12:54
> To: renba.chang@...
> Cc: sunilvl@...; tech-unixplatformspec@...;
> mchitale@...
> Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-
> spec: PLIC and CLINT for Linux-2022 platform
>
> On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:
> >
> >
> > Alistair Francis <Alistair.Francis@...> 2021524 週一
> > 上午11:42寫道:
> > > On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> > > > From: Abner Chang <renba.chang@...>
> > > >
> > > > Initial description of PLIC  CLINT section of Linux-2022 platform.
> > > >
> > > > Is this what we want to see of CLINT/Machine mode timer in the
> > > > platform spec?
> > > >
> > > > On v4 commit,
> > > > - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> > > > - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> > > > mention
> > > >   IPI because AIA already supported it.
> > > > - In Embedded-2022 Machine mode timer section, CLINT is not
> > > > mandatory.
> > > > - Separate section in appendix for the Machine mode timer
> > > > registers
> > > >
> > > > On v3 commit,
> > > > - Address review comments.
> > > >
> > > > On v2 commit,
> > > > - CLINT is not deprecated.
> > > >
> > > > - Add a standalone section for Machine Mode Timer in System
> > > > Peripherals.
> > > >   Do you think this is a good place for Machine Mode Timer?
> > > >   @Mayuresh, please check if you are ok with this change, not sure
> > > if
> > > > this
> > > >   overlaps with your text or not (The timer setion). I can remove
> > > > this
> > > >   if you prefer to put this with your patch.
> > > >
> > > > - In Embedded-2022, refer to Machine Mode Timer in System
> > > Peripherals
> > > >   section and CLINT in Linux-2022 Platform.
> > > >   @Alistair, is this ok?
> > > >
> > > > On v1 commit,
> > > > - Not sure where to put the [DEPRECATED].
> > > > - Change the reference of PLIC in section 2.2.2. Interrupt
> > > Controller
> > > > to
> > > >   1.1.3.2 PLIC + CLINT section.
> > > >
> > > > Signed-off-by: Abner Chang <renba.chang@...>
> > > > Cc: Alistair Francis <alistair.francis@...>
> > > > Cc: Sunil V L <sunilvl@...>
> > > > Cc: Mayuresh Chitale <mchitale@...>
> > > > ---
> > > >  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
> > > > --
> > > --
> > > > --
> > > >  1 file changed, 62 insertions(+), 42 deletions(-)
> > > >
> > > > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > > > index 160c74a..f8838ab 100644
> > > > --- a/riscv-platform-spec.adoc
> > > > +++ b/riscv-platform-spec.adoc
> > > > @@ -49,15 +49,37 @@ include::profiles.adoc[]
> > > >  * Start Address
> > > >
> > > >  ==== Interrupt Controller
> > > > -* AIA
> > > > -* PLIC + CLINT
> > > > -* Interrupt Assignments
> > > > +===== AIA[[AIA]]
> > > > +===== PLIC[DEPRECATED][[PLIC]]
> > > > +The Platform Level Interrupt Controller (PLIC) provides
> > > > facilities
> > > > to route
> > > > +the non-local interrupts to the external interrupt of a hart
> > > context
> > > > +with a given privilege mode in a given hart. The number of non-
> > > local
> > > > interrupt
> > > > +sources supported by PLIC and how does each of them connect to
> > > > the
> > > > hart
> > > > +context is PLIC core implementation-specific. + (Refer to
> > > >
> > > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc
> > > [RISC-V
> > > >  PLIC Specification]
> > > > +for the implementation reference of PLIC operation parameters)
> > > > +
> > > > +===== CLINT[[CLINT]]
> > > > +On the contrast to PLIC, the Core Local Interrupt (CLINT)
> > > > provides
> > >
> > > I don't think this is a contrast to the PLIC, it's just a different
> > > functionality.
> > >
> >
> > Can rephase it.
> > >
> > > I'm also not sure the CLINT should be in the interrupt controller
> > > section. It is the Core Local INTerruptor (CLINT), not an interrupt
> > > controller.
> > >
> >
> > Hmm.. CLINT is not a sort of interrupt controller but seems to me it
> > is unnecessary to create another section apart from the Interrupt
> > Controller section.
>
> It probably makes more sense to add a timer section and put the CLNIT there
> instead of forcing it into the interrupt controller section, when it isn't really an
> interrupt controller.
>
> > >
> > > > +facilities to trigger local interrupt of
> > > <<MachineModeTimer,Machine
> > > > mode timer>> to hart.
> > > > +
> > > > +===== Interrupt Assignments
> > > >
> > > >  ==== System Peripherals
> > > > -* UART/Serial Console
> > > > -* Clocks
> > > > -* Timers
> > > > -* Watchdog Timers
> > > > +===== UART/Serial Console
> > > > +===== Clocks
> > > > +===== Timers
> > > > +
> > > > +===== Machine Mode Timer[[MachineModeTimer]] Machine mode
> timer
> > > > +is required for Linux-2022 platform and
> > > > incorporate with
> > > > +<<CLINT,CLINT>> to trigger the timer event to hart. The format
> > > > of
> > > > Machine mode timer operation parameters
> > > > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> > >
> > > s/must compliant/must be compliant/g
> > >
> >
> > will correct this
> > >
> > > > Privilege specification section 3.1.10.
> > > > +The base address of the memory map registers of Machine mode
> > > > timer
> > > > is platform implementation-specific,
> > > > +however the offset of `mtime` and `mtimecmp` registers are fixed
> > > as
> > > > +<<machineModeTimerRegs,Machine mode timer registers>>.
> > > > +
> > > > +
> > > > +===== Watchdog Timers
> > > >
> > > >  ==== Boot Process
> > > >  * Firmware
> > > > @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
> > > can
> > > > meet the Embedded-2022
> > > >  specification.
> > > >
> > > >  ==== Interrupt Controller
> > > > -Embedded systems are recommended to use a spec compliant
> > > > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > > > -
> > > >
> > > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
> > > CLIC]
> > > > +Embedded systems are recommended to use a spec compliant
> > > > <<PLIC,PLIC>>, a spec
> > > > +compliant
> > > >
> > > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
> > > CLIC]
> > > >  or both a CLIC and and PLIC.
> > > >
> > > >  If using just a PLIC the system must continue to use the original
> > > > basic @@ -303,38 +324,9 @@ must be supported.
> > > >  Embedded systems cannot use a non-compliant interrupt controller
> > > and
> > > > still
> > > >  call it a PLIC or CLIC.
> > > >
> > > > -==== Machine Timer
> > > > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > > > must be -implemented. The two registers must be memory mapped as
> > > > required
> > > by
> > > > the RISC-V
> > > > -specification.
> > > > -
> > > > -The Embedded-2022 specification requires that the registers be
> > > > mapped -adjacent to each other with the `mtime` region at the
> > > > lower
> > > address.
> > > > -
> > > > -The starting address of this region can be located anywhere in
> > > > -memory, including inside other peripherals, as long as the start
> > > > address is
> > > > -4 byte aligned.
> > > > -
> > > > -An example of the memory layout for a 32-bit system with a single
> > > > hart is below
> > > > -
> > > > --------------------------
> > > > -=========================
> > > > -| 0x00 |  mtime low     |
> > > > -| 0x04 |  mtime high    |
> > > > -| 0x08 |  mtimecmp low  |
> > > > -| 0x0C |  mtimecmp high |
> > > > -=========================
> > > > --------------------------
> > > > -
> > > > -and for a 64-bit system with 2 harts
> > > > -
> > > > ----------------------------
> > > > -===========================
> > > > -| 0x00 |  mtime           |
> > > > -| 0x08 |  mtimecmp hart 1 |
> > > > -| 0x10 |  mtimecmp hart 2 |
> > > > -===========================
> > > > ----------------------------
> > > > +==== Machine Mode Timer
> > > > +The Embedded-2022 specification requires RISC-V
> > > > <<MachineModeTimer,Machine mode timer>> to be implemented.
> > > > +The Machine mode timer could be incorporated with the Core Local
> > > > Interrupt (<<CLINT, CLINT>>) or the specific event trigger
> > > mechanism
> > >
> > > CLINT is INTerruptor not just Interrupt.
> > >
> >
> > yes, will correct it
> > >
> > > > according to the platform design.
> > >
> > > What specific trigger mechanism?
> > >
> >
> > platform implementation-specific trigger mechanism?  or just remove
>
> I meant you didn't say what the mechanism is. It should be explicit, so that
> there are no ambiguities.
>
> > this? I put this just because the previous feedback says a small
> > system may not have CLINT for the m-mode timer.
>
> I would be in favour of saying either do what we already have written here OR
> a CLINT.
>
> If we go with something else that's ok, we just need to be clear about what it
> is.
>
> > >
> > > >
> > > >  ==== Memory Map
> > > >  It is recommended that main memory and loadable code (not ROM)
> > > start
> > > > at
> > > > @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> > > > include at least 4 regions, although
> > > >  if possible more should be supported to allow more flexibility.
> > > > Hardware
> > > >  implementations should aim for supporting at least 16 PMP
> > > > regions.
> > > >
> > > > +// Appendix sections
> > > > +== Appendix
> > > > +=== Machine Mode Timer Registers [[MachineModeTimerRegs]] The
> > > > +base address of Machine mode timer operation parameters is
> > > > platform implementation-specific. The Machine mode timer compare
> > > > registers (`mtimecmp`) for each hart is located at offset 0 and
> > > > the layout is organized as below table.
> > >
> > > Can we maintain what we have for the embedded spec?
> > >
> >
> > Do you mean to maintain the register layout(offset) originally defined
> > in the 2.2.3. for embedded systems?
>
> Yes. I worry that mandating a CLINT layout is too restrictive and that no one
> will end up following the embedded-2022 spec then. I would be in favour of
> saying CLINT or the memory layout we already have.

The ACLINT spec does not enforce any memory layout.
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc

The ACLINT is backward compatible to CLINT we should refer ACLINT
in-place of CLINT. This gives platform vendors flexibility to choose
their or memory layout and implement only certain parts of ACLINT
as required.

 

Hi Anup and Alistair. 

With ACLINT spec defined, I think we can revise this patch as below,

1.Remove CLINT from platform spec

2 Mention ACLINT in platform spec for Linux2020 platform and have a link to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.

3. Remove Machine mode timer from system peripheral because that is in the scope of ACLINT

4. For Embedded-2022 platform, mention Machine mode timer and refer to ACLINT for the definition of registers.

Any other thoughts?

 

Abner

 


Regards,
Anup

>
> > I think we have the register layout as below to be compliant with the
> > m-mode timer registers defined in SiFive CLINT.
>
> I don't think that's flexible enough and that vendors won't want to follow it as
> they already have other IP they are using for timers.
>
> Alistair
>
> > Or do you mean something else?
> >
> > >  It allows the
> > > memory maps to be inside of a MMIO device. For example they can be
> > > registers inside of a general system controller.
> > >
> > >
> > > Also it looks like the lines are a little long here, can be bring
> > > them back to 80 charecters?
> > >
> >
> > sure.
> > >
> > > > +
> > > > +.Registers layout of mtimecmp
> > > > +[width="60%",cols="1,^3,^3"]
> > > > +|=======
> > > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > > RV32*
> > > > +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > > > +|`0x0004` ||mtimecmp high for hart 0
> > > > +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > > > +|`0x000c` ||mtimecmp high for hart 1
> > > > +|... ||
> > > > +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > > > +|`0x7ff4` ||mtimecmp high for hart 4094
> > > > +|=======
> > > > +
> > > > +The Machine mode timer counter (`mtime`) is located at offset
> > > 0x7ff8
> > > > from the base address of operation parameters.
> > > > +
> > > > +.Registers layout of mtime
> > > > +[width="60%",cols="1,^3,^3"]
> > > > +|=======
> > > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > > RV32*
> > > > +|`0x7ff8` |mtime|mtime low
> > > > +|`0x7ffc` ||mtime high
> > > > +|=======
> > >
> > > Are you saying for a small embedded single core CPU we need to put
> > > mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
> > > addresses between them?
> > >
> > > Alistair
> > >
> > > > +
> > > >  // acknowledge all of the contributors
> > > >  include::contributors.adoc[]
> > >
>
>
>
>
>


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 



Anup Patel <Anup.Patel@...> 於 2021年5月25日 週二 下午12:39寫道:
Hi Alistar,

> -----Original Message-----
> From: tech-unixplatformspec@... <tech-
> unixplatformspec@...> On Behalf Of Alistair Francis
> Sent: 24 May 2021 12:54
> To: renba.chang@...
> Cc: sunilvl@...; tech-unixplatformspec@...;
> mchitale@...
> Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-
> spec: PLIC and CLINT for Linux-2022 platform
>
> On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:
> >
> >
> > Alistair Francis <Alistair.Francis@...> 於 2021年5月24日 週一
> > 上午11:42寫道:
> > > On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> > > > From: Abner Chang <renba.chang@...>
> > > >
> > > > Initial description of PLIC  CLINT section of Linux-2022 platform.
> > > >
> > > > Is this what we want to see of CLINT/Machine mode timer in the
> > > > platform spec?
> > > >
> > > > On v4 commit,
> > > > - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> > > > - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> > > > mention
> > > >   IPI because AIA already supported it.
> > > > - In Embedded-2022 Machine mode timer section, CLINT is not
> > > > mandatory.
> > > > - Separate section in appendix for the Machine mode timer
> > > > registers
> > > >
> > > > On v3 commit,
> > > > - Address review comments.
> > > >
> > > > On v2 commit,
> > > > - CLINT is not deprecated.
> > > >
> > > > - Add a standalone section for Machine Mode Timer in System
> > > > Peripherals.
> > > >   Do you think this is a good place for Machine Mode Timer?
> > > >   @Mayuresh, please check if you are ok with this change, not sure
> > > if
> > > > this
> > > >   overlaps with your text or not (The timer setion). I can remove
> > > > this
> > > >   if you prefer to put this with your patch.
> > > >
> > > > - In Embedded-2022, refer to Machine Mode Timer in System
> > > Peripherals
> > > >   section and CLINT in Linux-2022 Platform.
> > > >   @Alistair, is this ok?
> > > >
> > > > On v1 commit,
> > > > - Not sure where to put the [DEPRECATED].
> > > > - Change the reference of PLIC in section 2.2.2. Interrupt
> > > Controller
> > > > to
> > > >   1.1.3.2 PLIC + CLINT section.
> > > >
> > > > Signed-off-by: Abner Chang <renba.chang@...>
> > > > Cc: Alistair Francis <alistair.francis@...>
> > > > Cc: Sunil V L <sunilvl@...>
> > > > Cc: Mayuresh Chitale <mchitale@...>
> > > > ---
> > > >  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
> > > > --
> > > --
> > > > --
> > > >  1 file changed, 62 insertions(+), 42 deletions(-)
> > > >
> > > > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > > > index 160c74a..f8838ab 100644
> > > > --- a/riscv-platform-spec.adoc
> > > > +++ b/riscv-platform-spec.adoc
> > > > @@ -49,15 +49,37 @@ include::profiles.adoc[]
> > > >  * Start Address
> > > >
> > > >  ==== Interrupt Controller
> > > > -* AIA
> > > > -* PLIC + CLINT
> > > > -* Interrupt Assignments
> > > > +===== AIA[[AIA]]
> > > > +===== PLIC[DEPRECATED][[PLIC]]
> > > > +The Platform Level Interrupt Controller (PLIC) provides
> > > > facilities
> > > > to route
> > > > +the non-local interrupts to the external interrupt of a hart
> > > context
> > > > +with a given privilege mode in a given hart. The number of non-
> > > local
> > > > interrupt
> > > > +sources supported by PLIC and how does each of them connect to
> > > > the
> > > > hart
> > > > +context is PLIC core implementation-specific. + (Refer to
> > > >
> > > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc
> > > [RISC-V
> > > >  PLIC Specification]
> > > > +for the implementation reference of PLIC operation parameters)
> > > > +
> > > > +===== CLINT[[CLINT]]
> > > > +On the contrast to PLIC, the Core Local Interrupt (CLINT)
> > > > provides
> > >
> > > I don't think this is a contrast to the PLIC, it's just a different
> > > functionality.
> > >
> >
> > Can rephase it.
> > >
> > > I'm also not sure the CLINT should be in the interrupt controller
> > > section. It is the Core Local INTerruptor (CLINT), not an interrupt
> > > controller.
> > >
> >
> > Hmm.. CLINT is not a sort of interrupt controller but seems to me it
> > is unnecessary to create another section apart from the Interrupt
> > Controller section.
>
> It probably makes more sense to add a timer section and put the CLNIT there
> instead of forcing it into the interrupt controller section, when it isn't really an
> interrupt controller.
>
> > >
> > > > +facilities to trigger local interrupt of
> > > <<MachineModeTimer,Machine
> > > > mode timer>> to hart.
> > > > +
> > > > +===== Interrupt Assignments
> > > >
> > > >  ==== System Peripherals
> > > > -* UART/Serial Console
> > > > -* Clocks
> > > > -* Timers
> > > > -* Watchdog Timers
> > > > +===== UART/Serial Console
> > > > +===== Clocks
> > > > +===== Timers
> > > > +
> > > > +===== Machine Mode Timer[[MachineModeTimer]] Machine mode
> timer
> > > > +is required for Linux-2022 platform and
> > > > incorporate with
> > > > +<<CLINT,CLINT>> to trigger the timer event to hart. The format
> > > > of
> > > > Machine mode timer operation parameters
> > > > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> > >
> > > s/must compliant/must be compliant/g
> > >
> >
> > will correct this
> > >
> > > > Privilege specification section 3.1.10.
> > > > +The base address of the memory map registers of Machine mode
> > > > timer
> > > > is platform implementation-specific,
> > > > +however the offset of `mtime` and `mtimecmp` registers are fixed
> > > as
> > > > +<<machineModeTimerRegs,Machine mode timer registers>>.
> > > > +
> > > > +
> > > > +===== Watchdog Timers
> > > >
> > > >  ==== Boot Process
> > > >  * Firmware
> > > > @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
> > > can
> > > > meet the Embedded-2022
> > > >  specification.
> > > >
> > > >  ==== Interrupt Controller
> > > > -Embedded systems are recommended to use a spec compliant
> > > > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > > > -
> > > >
> > > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
> > > CLIC]
> > > > +Embedded systems are recommended to use a spec compliant
> > > > <<PLIC,PLIC>>, a spec
> > > > +compliant
> > > >
> > > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
> > > CLIC]
> > > >  or both a CLIC and and PLIC.
> > > >
> > > >  If using just a PLIC the system must continue to use the original
> > > > basic @@ -303,38 +324,9 @@ must be supported.
> > > >  Embedded systems cannot use a non-compliant interrupt controller
> > > and
> > > > still
> > > >  call it a PLIC or CLIC.
> > > >
> > > > -==== Machine Timer
> > > > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > > > must be -implemented. The two registers must be memory mapped as
> > > > required
> > > by
> > > > the RISC-V
> > > > -specification.
> > > > -
> > > > -The Embedded-2022 specification requires that the registers be
> > > > mapped -adjacent to each other with the `mtime` region at the
> > > > lower
> > > address.
> > > > -
> > > > -The starting address of this region can be located anywhere in
> > > > -memory, including inside other peripherals, as long as the start
> > > > address is
> > > > -4 byte aligned.
> > > > -
> > > > -An example of the memory layout for a 32-bit system with a single
> > > > hart is below
> > > > -
> > > > --------------------------
> > > > -=========================
> > > > -| 0x00 |  mtime low     |
> > > > -| 0x04 |  mtime high    |
> > > > -| 0x08 |  mtimecmp low  |
> > > > -| 0x0C |  mtimecmp high |
> > > > -=========================
> > > > --------------------------
> > > > -
> > > > -and for a 64-bit system with 2 harts
> > > > -
> > > > ----------------------------
> > > > -===========================
> > > > -| 0x00 |  mtime           |
> > > > -| 0x08 |  mtimecmp hart 1 |
> > > > -| 0x10 |  mtimecmp hart 2 |
> > > > -===========================
> > > > ----------------------------
> > > > +==== Machine Mode Timer
> > > > +The Embedded-2022 specification requires RISC-V
> > > > <<MachineModeTimer,Machine mode timer>> to be implemented.
> > > > +The Machine mode timer could be incorporated with the Core Local
> > > > Interrupt (<<CLINT, CLINT>>) or the specific event trigger
> > > mechanism
> > >
> > > CLINT is INTerruptor not just Interrupt.
> > >
> >
> > yes, will correct it
> > >
> > > > according to the platform design.
> > >
> > > What specific trigger mechanism?
> > >
> >
> > platform implementation-specific trigger mechanism?  or just remove
>
> I meant you didn't say what the mechanism is. It should be explicit, so that
> there are no ambiguities.
>
> > this? I put this just because the previous feedback says a small
> > system may not have CLINT for the m-mode timer.
>
> I would be in favour of saying either do what we already have written here OR
> a CLINT.
>
> If we go with something else that's ok, we just need to be clear about what it
> is.
>
> > >
> > > >
> > > >  ==== Memory Map
> > > >  It is recommended that main memory and loadable code (not ROM)
> > > start
> > > > at
> > > > @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> > > > include at least 4 regions, although
> > > >  if possible more should be supported to allow more flexibility.
> > > > Hardware
> > > >  implementations should aim for supporting at least 16 PMP
> > > > regions.
> > > >
> > > > +// Appendix sections
> > > > +== Appendix
> > > > +=== Machine Mode Timer Registers [[MachineModeTimerRegs]] The
> > > > +base address of Machine mode timer operation parameters is
> > > > platform implementation-specific. The Machine mode timer compare
> > > > registers (`mtimecmp`) for each hart is located at offset 0 and
> > > > the layout is organized as below table.
> > >
> > > Can we maintain what we have for the embedded spec?
> > >
> >
> > Do you mean to maintain the register layout(offset) originally defined
> > in the 2.2.3. for embedded systems?
>
> Yes. I worry that mandating a CLINT layout is too restrictive and that no one
> will end up following the embedded-2022 spec then. I would be in favour of
> saying CLINT or the memory layout we already have.

The ACLINT spec does not enforce any memory layout.
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc

The ACLINT is backward compatible to CLINT we should refer ACLINT
in-place of CLINT. This gives platform vendors flexibility to choose
their or memory layout and implement only certain parts of ACLINT
as required.

Hi Anup and Alistair. 
With ACLINT spec defined, I think we can revise this patch as below,
1.Remove CLINT from platform spec
2 Mention ACLINT in platform spec for Linux2020 platform and have a link to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc.
3. Remove Machine mode timer from system peripheral because that is in the scope of ACLINT
4. For Embedded-2022 platform, mention Machine mode timer and refer to ACLINT for the definition of registers.
Any other thoughts?

Abner


Regards,
Anup

>
> > I think we have the register layout as below to be compliant with the
> > m-mode timer registers defined in SiFive CLINT.
>
> I don't think that's flexible enough and that vendors won't want to follow it as
> they already have other IP they are using for timers.
>
> Alistair
>
> > Or do you mean something else?
> >
> > >  It allows the
> > > memory maps to be inside of a MMIO device. For example they can be
> > > registers inside of a general system controller.
> > >
> > >
> > > Also it looks like the lines are a little long here, can be bring
> > > them back to 80 charecters?
> > >
> >
> > sure.
> > >
> > > > +
> > > > +.Registers layout of mtimecmp
> > > > +[width="60%",cols="1,^3,^3"]
> > > > +|=======
> > > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > > RV32*
> > > > +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > > > +|`0x0004` ||mtimecmp high for hart 0
> > > > +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > > > +|`0x000c` ||mtimecmp high for hart 1
> > > > +|... ||
> > > > +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > > > +|`0x7ff4` ||mtimecmp high for hart 4094
> > > > +|=======
> > > > +
> > > > +The Machine mode timer counter (`mtime`) is located at offset
> > > 0x7ff8
> > > > from the base address of operation parameters.
> > > > +
> > > > +.Registers layout of mtime
> > > > +[width="60%",cols="1,^3,^3"]
> > > > +|=======
> > > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > > RV32*
> > > > +|`0x7ff8` |mtime|mtime low
> > > > +|`0x7ffc` ||mtime high
> > > > +|=======
> > >
> > > Are you saying for a small embedded single core CPU we need to put
> > > mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
> > > addresses between them?
> > >
> > > Alistair
> > >
> > > > +
> > > >  // acknowledge all of the contributors
> > > >  include::contributors.adoc[]
> > >
>
>
>
>
>


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Anup Patel
 

Hi Alistar,

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Alistair Francis
Sent: 24 May 2021 12:54
To: renba.chang@...
Cc: sunilvl@...; tech-unixplatformspec@...;
mchitale@...
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-
spec: PLIC and CLINT for Linux-2022 platform

On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:


Alistair Francis <Alistair.Francis@...> 於 2021年5月24日 週一
上午11:42寫道:
On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
mention
  IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not
mandatory.
- Separate section in appendix for the Machine mode timer
registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure
if
this
  overlaps with your text or not (The timer setion). I can remove
this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System
Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt
Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
--
--
--
 1 file changed, 62 insertions(+), 42 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..f8838ab 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,15 +49,37 @@ include::profiles.adoc[]
 * Start Address

 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides
facilities
to route
+the non-local interrupts to the external interrupt of a hart
context
+with a given privilege mode in a given hart. The number of non-
local
interrupt
+sources supported by PLIC and how does each of them connect to
the
hart
+context is PLIC core implementation-specific. + (Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc
[RISC-V
 PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== CLINT[[CLINT]]
+On the contrast to PLIC, the Core Local Interrupt (CLINT)
provides
I don't think this is a contrast to the PLIC, it's just a different
functionality.
Can rephase it.

I'm also not sure the CLINT should be in the interrupt controller
section. It is the Core Local INTerruptor (CLINT), not an interrupt
controller.
Hmm.. CLINT is not a sort of interrupt controller but seems to me it
is unnecessary to create another section apart from the Interrupt
Controller section.
It probably makes more sense to add a timer section and put the CLNIT there
instead of forcing it into the interrupt controller section, when it isn't really an
interrupt controller.


+facilities to trigger local interrupt of
<<MachineModeTimer,Machine
mode timer>> to hart.
+
+===== Interrupt Assignments

 ==== System Peripherals
-* UART/Serial Console
-* Clocks
-* Timers
-* Watchdog Timers
+===== UART/Serial Console
+===== Clocks
+===== Timers
+
+===== Machine Mode Timer[[MachineModeTimer]] Machine mode
timer
+is required for Linux-2022 platform and
incorporate with
+<<CLINT,CLINT>> to trigger the timer event to hart. The format
of
Machine mode timer operation parameters
+(`mtime` and `mtimecmp` registers) must compliant with RISC-V
s/must compliant/must be compliant/g
will correct this

Privilege specification section 3.1.10.
+The base address of the memory map registers of Machine mode
timer
is platform implementation-specific,
+however the offset of `mtime` and `mtimecmp` registers are fixed
as
+<<machineModeTimerRegs,Machine mode timer registers>>.
+
+
+===== Watchdog Timers

 ==== Boot Process
 * Firmware
@@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
can
meet the Embedded-2022
 specification.

 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
CLIC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>, a spec
+compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[
CLIC]
 or both a CLIC and and PLIC.

 If using just a PLIC the system must continue to use the original
basic @@ -303,38 +324,9 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller
and
still
 call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
must be -implemented. The two registers must be memory mapped as
required
by
the RISC-V
-specification.
-
-The Embedded-2022 specification requires that the registers be
mapped -adjacent to each other with the `mtime` region at the
lower
address.
-
-The starting address of this region can be located anywhere in
-memory, including inside other peripherals, as long as the start
address is
-4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single
hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
----------------------------
+==== Machine Mode Timer
+The Embedded-2022 specification requires RISC-V
<<MachineModeTimer,Machine mode timer>> to be implemented.
+The Machine mode timer could be incorporated with the Core Local
Interrupt (<<CLINT, CLINT>>) or the specific event trigger
mechanism

CLINT is INTerruptor not just Interrupt.
yes, will correct it

according to the platform design.
What specific trigger mechanism?
platform implementation-specific trigger mechanism?  or just remove
I meant you didn't say what the mechanism is. It should be explicit, so that
there are no ambiguities.

this? I put this just because the previous feedback says a small
system may not have CLINT for the m-mode timer.
I would be in favour of saying either do what we already have written here OR
a CLINT.

If we go with something else that's ok, we just need to be clear about what it
is.



 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM)
start
at
@@ -349,5 +341,33 @@ When PMP is supported it is recommended to
include at least 4 regions, although
 if possible more should be supported to allow more flexibility.
Hardware
 implementations should aim for supporting at least 16 PMP
regions.

+// Appendix sections
+== Appendix
+=== Machine Mode Timer Registers [[MachineModeTimerRegs]] The
+base address of Machine mode timer operation parameters is
platform implementation-specific. The Machine mode timer compare
registers (`mtimecmp`) for each hart is located at offset 0 and
the layout is organized as below table.
Can we maintain what we have for the embedded spec?
Do you mean to maintain the register layout(offset) originally defined
in the 2.2.3. for embedded systems?
Yes. I worry that mandating a CLINT layout is too restrictive and that no one
will end up following the embedded-2022 spec then. I would be in favour of
saying CLINT or the memory layout we already have.
The ACLINT spec does not enforce any memory layout.
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc

The ACLINT is backward compatible to CLINT we should refer ACLINT
in-place of CLINT. This gives platform vendors flexibility to choose
their or memory layout and implement only certain parts of ACLINT
as required.

Regards,
Anup


I think we have the register layout as below to be compliant with the
m-mode timer registers defined in SiFive CLINT.
I don't think that's flexible enough and that vendors won't want to follow it as
they already have other IP they are using for timers.

Alistair

Or do you mean something else?

 It allows the
memory maps to be inside of a MMIO device. For example they can be
registers inside of a general system controller.


Also it looks like the lines are a little long here, can be bring
them back to 80 charecters?
sure.

+
+.Registers layout of mtimecmp
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
RV32*
+|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
+|`0x0004` ||mtimecmp high for hart 0
+|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
+|`0x000c` ||mtimecmp high for hart 1
+|... ||
+|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
+|`0x7ff4` ||mtimecmp high for hart 4094
+|=======
+
+The Machine mode timer counter (`mtime`) is located at offset
0x7ff8
from the base address of operation parameters.
+
+.Registers layout of mtime
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
RV32*
+|`0x7ff8` |mtime|mtime low
+|`0x7ffc` ||mtime high
+|=======
Are you saying for a small embedded single core CPU we need to put
mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
addresses between them?

Alistair

+
 // acknowledge all of the contributors
 include::contributors.adoc[]




Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Anup Patel
 

Hi Abner,

 

Yesterday, we move ACLINT spec under the RISC-V International GitHub.

 

New link of the ACLINT spec is:

https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc

 

You can even clone https://github.com/riscv/riscv-aclint.git and build a PDF version of the ACLINT spec.

 

Regards,

Anup

 

From: tech-unixplatformspec@... <tech-unixplatformspec@...> On Behalf Of Abner Chang
Sent: 25 May 2021 09:47
To: Alistair Francis <Alistair.Francis@...>
Cc: sunilvl@...; tech-unixplatformspec@...; mchitale@...
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

 

 

Alistair Francis <Alistair.Francis@...> 2021524 週一 下午3:23寫道:

On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:
>
>
> Alistair Francis <Alistair.Francis@...> 2021524 週一
> 上午11:42寫道:
> > On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> > > From: Abner Chang <renba.chang@...>
> > >
> > > Initial description of PLIC  CLINT section of Linux-2022
> > > platform.
> > >
> > > Is this what we want to see of CLINT/Machine mode timer in the
> > > platform spec?
> > >
> > > On v4 commit,
> > > - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> > > - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> > > mention
> > >   IPI because AIA already supported it.
> > > - In Embedded-2022 Machine mode timer section, CLINT is not
> > > mandatory.
> > > - Separate section in appendix for the Machine mode timer
> > > registers
> > >
> > > On v3 commit,
> > > - Address review comments.
> > >
> > > On v2 commit,
> > > - CLINT is not deprecated.
> > >
> > > - Add a standalone section for Machine Mode Timer in System
> > > Peripherals.
> > >   Do you think this is a good place for Machine Mode Timer?
> > >   @Mayuresh, please check if you are ok with this change, not
> > > sure
> > if
> > > this
> > >   overlaps with your text or not (The timer setion). I can remove
> > > this
> > >   if you prefer to put this with your patch.
> > >
> > > - In Embedded-2022, refer to Machine Mode Timer in System
> > Peripherals
> > >   section and CLINT in Linux-2022 Platform.
> > >   @Alistair, is this ok?
> > >
> > > On v1 commit,
> > > - Not sure where to put the [DEPRECATED].
> > > - Change the reference of PLIC in section 2.2.2. Interrupt
> > Controller
> > > to
> > >   1.1.3.2 PLIC + CLINT section.
> > >
> > > Signed-off-by: Abner Chang <renba.chang@...>
> > > Cc: Alistair Francis <alistair.francis@...>
> > > Cc: Sunil V L <sunilvl@...>
> > > Cc: Mayuresh Chitale <mchitale@...>
> > > ---
> > >  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
> > > --
> > --
> > > --
> > >  1 file changed, 62 insertions(+), 42 deletions(-)
> > >
> > > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > > index 160c74a..f8838ab 100644
> > > --- a/riscv-platform-spec.adoc
> > > +++ b/riscv-platform-spec.adoc
> > > @@ -49,15 +49,37 @@ include::profiles.adoc[]
> > >  * Start Address
> > >  
> > >  ==== Interrupt Controller
> > > -* AIA
> > > -* PLIC + CLINT
> > > -* Interrupt Assignments
> > > +===== AIA[[AIA]]
> > > +===== PLIC[DEPRECATED][[PLIC]]
> > > +The Platform Level Interrupt Controller (PLIC) provides
> > > facilities
> > > to route
> > > +the non-local interrupts to the external interrupt of a hart
> > context
> > > +with a given privilege mode in a given hart. The number of non-
> > local
> > > interrupt
> > > +sources supported by PLIC and how does each of them connect to
> > > the
> > > hart
> > > +context is PLIC core implementation-specific. +
> > > +(Refer to   
> > >
> > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
> > >  PLIC Specification]
> > > +for the implementation reference of PLIC operation parameters)
> > > +
> > > +===== CLINT[[CLINT]]
> > > +On the contrast to PLIC, the Core Local Interrupt (CLINT)
> > > provides
> >
> > I don't think this is a contrast to the PLIC, it's just a different
> > functionality.
> >
>
> Can rephase it. 
> >
> > I'm also not sure the CLINT should be in the interrupt controller
> > section. It is the Core Local INTerruptor (CLINT), not an interrupt
> > controller.
> >
>
> Hmm.. CLINT is not a sort of interrupt controller but seems to me it
> is unnecessary to create another section apart from the Interrupt
> Controller section.

It probably makes more sense to add a timer section and put the CLNIT
there instead of forcing it into the interrupt controller section, when
it isn't really an interrupt controller.

> >
> > > +facilities to trigger local interrupt of
> > <<MachineModeTimer,Machine
> > > mode timer>> to hart.
> > > +
> > > +===== Interrupt Assignments
> > >  
> > >  ==== System Peripherals
> > > -* UART/Serial Console
> > > -* Clocks
> > > -* Timers
> > > -* Watchdog Timers
> > > +===== UART/Serial Console
> > > +===== Clocks
> > > +===== Timers
> > > +
> > > +===== Machine Mode Timer[[MachineModeTimer]]
> > > +Machine mode timer is required for Linux-2022 platform and
> > > incorporate with
> > > +<<CLINT,CLINT>> to trigger the timer event to hart. The format
> > > of
> > > Machine mode timer operation parameters
> > > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> >
> > s/must compliant/must be compliant/g
> >
>
> will correct this 
> >
> > > Privilege specification section 3.1.10.
> > > +The base address of the memory map registers of Machine mode
> > > timer
> > > is platform implementation-specific,
> > > +however the offset of `mtime` and `mtimecmp` registers are fixed
> > as
> > > +<<machineModeTimerRegs,Machine mode timer registers>>.
> > > +
> > > +
> > > +===== Watchdog Timers
> > >  
> > >  ==== Boot Process
> > >  * Firmware
> > > @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
> > can
> > > meet the Embedded-2022
> > >  specification.
> > >  
> > >  ==== Interrupt Controller
> > > -Embedded systems are recommended to use a spec compliant
> > > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > > -       
> > >
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > > +Embedded systems are recommended to use a spec compliant
> > > <<PLIC,PLIC>>, a spec
> > > +compliant         
> > >
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > >  or both a CLIC and and PLIC.
> > >  
> > >  If using just a PLIC the system must continue to use the
> > > original
> > > basic
> > > @@ -303,38 +324,9 @@ must be supported.
> > >  Embedded systems cannot use a non-compliant interrupt controller
> > and
> > > still
> > >  call it a PLIC or CLIC.
> > >  
> > > -==== Machine Timer
> > > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > > must be
> > > -implemented. The two registers must be memory mapped as required
> > by
> > > the RISC-V
> > > -specification.
> > > -
> > > -The Embedded-2022 specification requires that the registers be
> > > mapped
> > > -adjacent to each other with the `mtime` region at the lower
> > address.
> > > -
> > > -The starting address of this region can be located anywhere in
> > > -memory, including inside other peripherals, as long as the start
> > > address is
> > > -4 byte aligned.
> > > -
> > > -An example of the memory layout for a 32-bit system with a
> > > single
> > > hart is below
> > > -
> > > --------------------------
> > > -=========================
> > > -| 0x00 |  mtime low     |
> > > -| 0x04 |  mtime high    |
> > > -| 0x08 |  mtimecmp low  |
> > > -| 0x0C |  mtimecmp high |
> > > -=========================
> > > --------------------------
> > > -
> > > -and for a 64-bit system with 2 harts
> > > -
> > > ----------------------------
> > > -===========================
> > > -| 0x00 |  mtime           |
> > > -| 0x08 |  mtimecmp hart 1 |
> > > -| 0x10 |  mtimecmp hart 2 |
> > > -===========================
> > > ----------------------------
> > > +==== Machine Mode Timer
> > > +The Embedded-2022 specification requires RISC-V
> > > <<MachineModeTimer,Machine mode timer>> to be implemented.
> > > +The Machine mode timer could be incorporated with the Core Local
> > > Interrupt (<<CLINT, CLINT>>) or the specific event trigger
> > mechanism
> >
> > CLINT is INTerruptor not just Interrupt.
> >
>
> yes, will correct it
> >
> > > according to the platform design.
> >
> > What specific trigger mechanism?
> >
>
> platform implementation-specific trigger mechanism?  or just remove

I meant you didn't say what the mechanism is. It should be explicit, so
that there are no ambiguities.

> this? I put this just because the previous feedback says a small
> system may not have CLINT for the m-mode timer.

I would be in favour of saying either do what we already have written
here OR a CLINT.

If we go with something else that's ok, we just need to be clear about
what it is.

> >
> > >  
> > >  ==== Memory Map
> > >  It is recommended that main memory and loadable code (not ROM)
> > start
> > > at
> > > @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> > > include at least 4 regions, although
> > >  if possible more should be supported to allow more flexibility.
> > > Hardware
> > >  implementations should aim for supporting at least 16 PMP
> > > regions.
> > >  
> > > +// Appendix sections
> > > +== Appendix
> > > +=== Machine Mode Timer Registers [[MachineModeTimerRegs]]
> > > +The base address of Machine mode timer operation parameters is
> > > platform implementation-specific. The Machine mode timer compare
> > > registers (`mtimecmp`) for each hart is located at offset 0 and
> > > the
> > > layout is organized as below table.
> >
> > Can we maintain what we have for the embedded spec?
> >
>
> Do you mean to maintain the register layout(offset) originally
> defined in the 2.2.3. for embedded systems? 

Yes. I worry that mandating a CLINT layout is too restrictive and that
no one will end up following the embedded-2022 spec then. I would be in
favour of saying CLINT or the memory layout we already have.

> I think we have the register layout as below to be compliant with the
> m-mode timer registers defined in SiFive CLINT.

I don't think that's flexible enough and that vendors won't want to
follow it as they already have other IP they are using for timers.

Alistair

 

I will remove CLINT from this patch. 

@Anup, how do you define the MTIME registers in ACLINT? Can we just define the base address for both mtimecmp and mtime thus we can have 0 based offset?

 

Abner

 


> Or do you mean something else?
>
> >  It allows the
> > memory maps to be inside of a MMIO device. For example they can be
> > registers inside of a general system controller.
> >
> >
> > Also it looks like the lines are a little long here, can be bring
> > them
> > back to 80 charecters?
> >
>
> sure. 
> >
> > > +
> > > +.Registers layout of mtimecmp
> > > +[width="60%",cols="1,^3,^3"]
> > > +|=======
> > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > > +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > > +|`0x0004` ||mtimecmp high for hart 0
> > > +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > > +|`0x000c` ||mtimecmp high for hart 1
> > > +|... ||
> > > +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > > +|`0x7ff4` ||mtimecmp high for hart 4094
> > > +|=======
> > > +
> > > +The Machine mode timer counter (`mtime`) is located at offset
> > 0x7ff8
> > > from the base address of operation parameters.
> > > +
> > > +.Registers layout of mtime
> > > +[width="60%",cols="1,^3,^3"]
> > > +|=======
> > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > > +|`0x7ff8` |mtime|mtime low
> > > +|`0x7ffc` ||mtime high
> > > +|=======
> >
> > Are you saying for a small embedded single core CPU we need to put
> > mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
> > addresses between them?
> >
> > Alistair
> >
> > > +
> > >  // acknowledge all of the contributors
> > >  include::contributors.adoc[]
> >


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 



Alistair Francis <Alistair.Francis@...> 於 2021年5月24日 週一 下午3:23寫道:
On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:
>
>
> Alistair Francis <Alistair.Francis@...> 於 2021年5月24日 週一
> 上午11:42寫道:
> > On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> > > From: Abner Chang <renba.chang@...>
> > >
> > > Initial description of PLIC  CLINT section of Linux-2022
> > > platform.
> > >
> > > Is this what we want to see of CLINT/Machine mode timer in the
> > > platform spec?
> > >
> > > On v4 commit,
> > > - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> > > - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> > > mention
> > >   IPI because AIA already supported it.
> > > - In Embedded-2022 Machine mode timer section, CLINT is not
> > > mandatory.
> > > - Separate section in appendix for the Machine mode timer
> > > registers
> > >
> > > On v3 commit,
> > > - Address review comments.
> > >
> > > On v2 commit,
> > > - CLINT is not deprecated.
> > >
> > > - Add a standalone section for Machine Mode Timer in System
> > > Peripherals.
> > >   Do you think this is a good place for Machine Mode Timer?
> > >   @Mayuresh, please check if you are ok with this change, not
> > > sure
> > if
> > > this
> > >   overlaps with your text or not (The timer setion). I can remove
> > > this
> > >   if you prefer to put this with your patch.
> > >
> > > - In Embedded-2022, refer to Machine Mode Timer in System
> > Peripherals
> > >   section and CLINT in Linux-2022 Platform.
> > >   @Alistair, is this ok?
> > >
> > > On v1 commit,
> > > - Not sure where to put the [DEPRECATED].
> > > - Change the reference of PLIC in section 2.2.2. Interrupt
> > Controller
> > > to
> > >   1.1.3.2 PLIC + CLINT section.
> > >
> > > Signed-off-by: Abner Chang <renba.chang@...>
> > > Cc: Alistair Francis <alistair.francis@...>
> > > Cc: Sunil V L <sunilvl@...>
> > > Cc: Mayuresh Chitale <mchitale@...>
> > > ---
> > >  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
> > > --
> > --
> > > --
> > >  1 file changed, 62 insertions(+), 42 deletions(-)
> > >
> > > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > > index 160c74a..f8838ab 100644
> > > --- a/riscv-platform-spec.adoc
> > > +++ b/riscv-platform-spec.adoc
> > > @@ -49,15 +49,37 @@ include::profiles.adoc[]
> > >  * Start Address
> > >  
> > >  ==== Interrupt Controller
> > > -* AIA
> > > -* PLIC + CLINT
> > > -* Interrupt Assignments
> > > +===== AIA[[AIA]]
> > > +===== PLIC[DEPRECATED][[PLIC]]
> > > +The Platform Level Interrupt Controller (PLIC) provides
> > > facilities
> > > to route
> > > +the non-local interrupts to the external interrupt of a hart
> > context
> > > +with a given privilege mode in a given hart. The number of non-
> > local
> > > interrupt
> > > +sources supported by PLIC and how does each of them connect to
> > > the
> > > hart
> > > +context is PLIC core implementation-specific. +
> > > +(Refer to   
> > >
> > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
> > >  PLIC Specification]
> > > +for the implementation reference of PLIC operation parameters)
> > > +
> > > +===== CLINT[[CLINT]]
> > > +On the contrast to PLIC, the Core Local Interrupt (CLINT)
> > > provides
> >
> > I don't think this is a contrast to the PLIC, it's just a different
> > functionality.
> >
>
> Can rephase it. 
> >
> > I'm also not sure the CLINT should be in the interrupt controller
> > section. It is the Core Local INTerruptor (CLINT), not an interrupt
> > controller.
> >
>
> Hmm.. CLINT is not a sort of interrupt controller but seems to me it
> is unnecessary to create another section apart from the Interrupt
> Controller section.

It probably makes more sense to add a timer section and put the CLNIT
there instead of forcing it into the interrupt controller section, when
it isn't really an interrupt controller.

> >
> > > +facilities to trigger local interrupt of
> > <<MachineModeTimer,Machine
> > > mode timer>> to hart.
> > > +
> > > +===== Interrupt Assignments
> > >  
> > >  ==== System Peripherals
> > > -* UART/Serial Console
> > > -* Clocks
> > > -* Timers
> > > -* Watchdog Timers
> > > +===== UART/Serial Console
> > > +===== Clocks
> > > +===== Timers
> > > +
> > > +===== Machine Mode Timer[[MachineModeTimer]]
> > > +Machine mode timer is required for Linux-2022 platform and
> > > incorporate with
> > > +<<CLINT,CLINT>> to trigger the timer event to hart. The format
> > > of
> > > Machine mode timer operation parameters
> > > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> >
> > s/must compliant/must be compliant/g
> >
>
> will correct this 
> >
> > > Privilege specification section 3.1.10.
> > > +The base address of the memory map registers of Machine mode
> > > timer
> > > is platform implementation-specific,
> > > +however the offset of `mtime` and `mtimecmp` registers are fixed
> > as
> > > +<<machineModeTimerRegs,Machine mode timer registers>>.
> > > +
> > > +
> > > +===== Watchdog Timers
> > >  
> > >  ==== Boot Process
> > >  * Firmware
> > > @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
> > can
> > > meet the Embedded-2022
> > >  specification.
> > >  
> > >  ==== Interrupt Controller
> > > -Embedded systems are recommended to use a spec compliant
> > > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > > -       
> > >
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > > +Embedded systems are recommended to use a spec compliant
> > > <<PLIC,PLIC>>, a spec
> > > +compliant         
> > >
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > >  or both a CLIC and and PLIC.
> > >  
> > >  If using just a PLIC the system must continue to use the
> > > original
> > > basic
> > > @@ -303,38 +324,9 @@ must be supported.
> > >  Embedded systems cannot use a non-compliant interrupt controller
> > and
> > > still
> > >  call it a PLIC or CLIC.
> > >  
> > > -==== Machine Timer
> > > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > > must be
> > > -implemented. The two registers must be memory mapped as required
> > by
> > > the RISC-V
> > > -specification.
> > > -
> > > -The Embedded-2022 specification requires that the registers be
> > > mapped
> > > -adjacent to each other with the `mtime` region at the lower
> > address.
> > > -
> > > -The starting address of this region can be located anywhere in
> > > -memory, including inside other peripherals, as long as the start
> > > address is
> > > -4 byte aligned.
> > > -
> > > -An example of the memory layout for a 32-bit system with a
> > > single
> > > hart is below
> > > -
> > > --------------------------
> > > -=========================
> > > -| 0x00 |  mtime low     |
> > > -| 0x04 |  mtime high    |
> > > -| 0x08 |  mtimecmp low  |
> > > -| 0x0C |  mtimecmp high |
> > > -=========================
> > > --------------------------
> > > -
> > > -and for a 64-bit system with 2 harts
> > > -
> > > ----------------------------
> > > -===========================
> > > -| 0x00 |  mtime           |
> > > -| 0x08 |  mtimecmp hart 1 |
> > > -| 0x10 |  mtimecmp hart 2 |
> > > -===========================
> > > ----------------------------
> > > +==== Machine Mode Timer
> > > +The Embedded-2022 specification requires RISC-V
> > > <<MachineModeTimer,Machine mode timer>> to be implemented.
> > > +The Machine mode timer could be incorporated with the Core Local
> > > Interrupt (<<CLINT, CLINT>>) or the specific event trigger
> > mechanism
> >
> > CLINT is INTerruptor not just Interrupt.
> >
>
> yes, will correct it
> >
> > > according to the platform design.
> >
> > What specific trigger mechanism?
> >
>
> platform implementation-specific trigger mechanism?  or just remove

I meant you didn't say what the mechanism is. It should be explicit, so
that there are no ambiguities.

> this? I put this just because the previous feedback says a small
> system may not have CLINT for the m-mode timer.

I would be in favour of saying either do what we already have written
here OR a CLINT.

If we go with something else that's ok, we just need to be clear about
what it is.

> >
> > >  
> > >  ==== Memory Map
> > >  It is recommended that main memory and loadable code (not ROM)
> > start
> > > at
> > > @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> > > include at least 4 regions, although
> > >  if possible more should be supported to allow more flexibility.
> > > Hardware
> > >  implementations should aim for supporting at least 16 PMP
> > > regions.
> > >  
> > > +// Appendix sections
> > > +== Appendix
> > > +=== Machine Mode Timer Registers [[MachineModeTimerRegs]]
> > > +The base address of Machine mode timer operation parameters is
> > > platform implementation-specific. The Machine mode timer compare
> > > registers (`mtimecmp`) for each hart is located at offset 0 and
> > > the
> > > layout is organized as below table.
> >
> > Can we maintain what we have for the embedded spec?
> >
>
> Do you mean to maintain the register layout(offset) originally
> defined in the 2.2.3. for embedded systems? 

Yes. I worry that mandating a CLINT layout is too restrictive and that
no one will end up following the embedded-2022 spec then. I would be in
favour of saying CLINT or the memory layout we already have.

> I think we have the register layout as below to be compliant with the
> m-mode timer registers defined in SiFive CLINT.

I don't think that's flexible enough and that vendors won't want to
follow it as they already have other IP they are using for timers.

Alistair

I will remove CLINT from this patch. 
@Anup, how do you define the MTIME registers in ACLINT? Can we just define the base address for both mtimecmp and mtime thus we can have 0 based offset?

Abner


> Or do you mean something else?
>
> >  It allows the
> > memory maps to be inside of a MMIO device. For example they can be
> > registers inside of a general system controller.
> >
> >
> > Also it looks like the lines are a little long here, can be bring
> > them
> > back to 80 charecters?
> >
>
> sure. 
> >
> > > +
> > > +.Registers layout of mtimecmp
> > > +[width="60%",cols="1,^3,^3"]
> > > +|=======
> > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > > +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > > +|`0x0004` ||mtimecmp high for hart 0
> > > +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > > +|`0x000c` ||mtimecmp high for hart 1
> > > +|... ||
> > > +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > > +|`0x7ff4` ||mtimecmp high for hart 4094
> > > +|=======
> > > +
> > > +The Machine mode timer counter (`mtime`) is located at offset
> > 0x7ff8
> > > from the base address of operation parameters.
> > > +
> > > +.Registers layout of mtime
> > > +[width="60%",cols="1,^3,^3"]
> > > +|=======
> > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > > +|`0x7ff8` |mtime|mtime low
> > > +|`0x7ffc` ||mtime high
> > > +|=======
> >
> > Are you saying for a small embedded single core CPU we need to put
> > mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
> > addresses between them?
> >
> > Alistair
> >
> > > +
> > >  // acknowledge all of the contributors
> > >  include::contributors.adoc[]
> >


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 



Anup Patel <Anup.Patel@...> 於 2021年5月24日 週一 下午3:43寫道:


> -----Original Message-----
> From: tech-unixplatformspec@... <tech-
> unixplatformspec@...> On Behalf Of Abner Chang
> Sent: 24 May 2021 08:34
> To: tech-unixplatformspec@...
> Cc: Alistair Francis <Alistair.Francis@...>; Sunil V L
> <sunilvl@...>; Mayuresh Chitale
> <mchitale@...>
> Subject: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-spec:
> PLIC and CLINT for Linux-2022 platform
>
> From: Abner Chang <renba.chang@...>
>
> Initial description of PLIC  CLINT section of Linux-2022 platform.
>
> Is this what we want to see of CLINT/Machine mode timer in the platform
> spec?
>
> On v4 commit,
> - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> - CLINT section in Linux- 2022 chapter for M-mode timer. We don't mention
>   IPI because AIA already supported it.
> - In Embedded-2022 Machine mode timer section, CLINT is not mandatory.
> - Separate section in appendix for the Machine mode timer registers
>
> On v3 commit,
> - Address review comments.
>
> On v2 commit,
> - CLINT is not deprecated.
>
> - Add a standalone section for Machine Mode Timer in System Peripherals.
>   Do you think this is a good place for Machine Mode Timer?
>   @Mayuresh, please check if you are ok with this change, not sure if this
>   overlaps with your text or not (The timer setion). I can remove this
>   if you prefer to put this with your patch.
>
> - In Embedded-2022, refer to Machine Mode Timer in System Peripherals
>   section and CLINT in Linux-2022 Platform.
>   @Alistair, is this ok?
>
> On v1 commit,
> - Not sure where to put the [DEPRECATED].
> - Change the reference of PLIC in section 2.2.2. Interrupt Controller to
>   1.1.3.2 PLIC + CLINT section.
>
> Signed-off-by: Abner Chang <renba.chang@...>
> Cc: Alistair Francis <alistair.francis@...>
> Cc: Sunil V L <sunilvl@...>
> Cc: Mayuresh Chitale <mchitale@...>
> ---
>  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------------
>  1 file changed, 62 insertions(+), 42 deletions(-)
>
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index
> 160c74a..f8838ab 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -49,15 +49,37 @@ include::profiles.adoc[]
>  * Start Address
>
>  ==== Interrupt Controller
> -* AIA
> -* PLIC + CLINT
> -* Interrupt Assignments
> +===== AIA[[AIA]]
> +===== PLIC[DEPRECATED][[PLIC]]
> +The Platform Level Interrupt Controller (PLIC) provides facilities to
> +route the non-local interrupts to the external interrupt of a hart
> +context with a given privilege mode in a given hart. The number of
> +non-local interrupt sources supported by PLIC and how does each of them
> +connect to the hart context is PLIC core implementation-specific. +
> +(Refer to
> +https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RI
> +SC-V PLIC Specification] for the implementation reference of PLIC
> +operation parameters)
> +
> +===== CLINT[[CLINT]]
> +On the contrast to PLIC, the Core Local Interrupt (CLINT) provides
> +facilities to trigger local interrupt of <<MachineModeTimer,Machine mode
> timer>> to hart.

We don't need a CLINT chapter in platform specification anymore.

Instead, we are proposing an Advanced CLINT (or ACLINT) which is:
1) Backward compatible with SiFive CLINT hence existing systems
     will be compliant with new ACLINT spec
2) More modular compared to original CLINT and each functionality
     is defined as a distinct device
3) Provision for S-mode software interrupts
4) Allow multi-socket (or mult-die) systems with multiple MTIMER,
     MSWI, and SSWI devices defined by ACLINT spec.

The ACLINT helps us complete the IPI and Timer story for BASE
and Server platforms. Also, being backward compatible with SiFive
CLINT we don't need to point to define CLINT in platform spec.
This is good, may fix some controversies.

The latest proposal of ACLINT spec is at:
https://github.com/avpatel/riscv-aclint-doc/blob/master/riscv-aclint.adoc
Is this link valid or not public?


The ACLINT proposal was discussed in past platform meeting and
past AIA meeting as well.

Eventually, the ACLINT spec will be owned by RISC-V international
and hosted on RISC-V Github.

@Andrew Waterman can you please review ACLINT proposal ?

Regards,
Anup

> +
> +===== Interrupt Assignments
>
>  ==== System Peripherals
> -* UART/Serial Console
> -* Clocks
> -* Timers
> -* Watchdog Timers
> +===== UART/Serial Console
> +===== Clocks
> +===== Timers
> +
> +===== Machine Mode Timer[[MachineModeTimer]] Machine mode timer is
> +required for Linux-2022 platform and incorporate with <<CLINT,CLINT>>
> +to trigger the timer event to hart. The format of Machine mode timer
> +operation parameters (`mtime` and `mtimecmp` registers) must compliant
> with RISC-V Privilege specification section 3.1.10.
> +The base address of the memory map registers of Machine mode timer is
> +platform implementation-specific, however the offset of `mtime` and
> +`mtimecmp` registers are fixed as <<machineModeTimerRegs,Machine mode
> timer registers>>.
> +
> +
> +===== Watchdog Timers
>
>  ==== Boot Process
>  * Firmware
> @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G can
> meet the Embedded-2022  specification.
>
>  ==== Interrupt Controller
> -Embedded systems are recommended to use a spec compliant -
> https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant -
> https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> +Embedded systems are recommended to use a spec compliant
> <<PLIC,PLIC>>,
> +a spec compliant
> +https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLI
> +C]
>  or both a CLIC and and PLIC.
>
>  If using just a PLIC the system must continue to use the original basic @@ -
> 303,38 +324,9 @@ must be supported.
>  Embedded systems cannot use a non-compliant interrupt controller and still
> call it a PLIC or CLIC.
>
> -==== Machine Timer
> -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must be -
> implemented. The two registers must be memory mapped as required by the
> RISC-V -specification.
> -
> -The Embedded-2022 specification requires that the registers be mapped -
> adjacent to each other with the `mtime` region at the lower address.
> -
> -The starting address of this region can be located anywhere in -memory,
> including inside other peripherals, as long as the start address is
> -4 byte aligned.
> -
> -An example of the memory layout for a 32-bit system with a single hart is
> below
> -
> --------------------------
> -=========================
> -| 0x00 |  mtime low     |
> -| 0x04 |  mtime high    |
> -| 0x08 |  mtimecmp low  |
> -| 0x0C |  mtimecmp high |
> -=========================
> --------------------------
> -
> -and for a 64-bit system with 2 harts
> -
> ----------------------------
> -===========================
> -| 0x00 |  mtime           |
> -| 0x08 |  mtimecmp hart 1 |
> -| 0x10 |  mtimecmp hart 2 |
> -===========================
> ----------------------------
> +==== Machine Mode Timer
> +The Embedded-2022 specification requires RISC-V
> <<MachineModeTimer,Machine mode timer>> to be implemented.
> +The Machine mode timer could be incorporated with the Core Local
> Interrupt (<<CLINT, CLINT>>) or the specific event trigger mechanism
> according to the platform design.
>
>  ==== Memory Map
>  It is recommended that main memory and loadable code (not ROM) start at
> @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> include at least 4 regions, although  if possible more should be supported to
> allow more flexibility. Hardware  implementations should aim for supporting
> at least 16 PMP regions.
>
> +// Appendix sections
> +== Appendix
> +=== Machine Mode Timer Registers [[MachineModeTimerRegs]] The base
> +address of Machine mode timer operation parameters is platform
> implementation-specific. The Machine mode timer compare registers
> (`mtimecmp`) for each hart is located at offset 0 and the layout is organized
> as below table.
> +
> +.Registers layout of mtimecmp
> +[width="60%",cols="1,^3,^3"]
> +|=======
> +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
> +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0 `0x0004`
> +|||mtimecmp high for hart 0 `0x0008` |mtimecmp for hart 1 |mtimecmp
> low
> +|for hart 1 `0x000c` ||mtimecmp high for hart 1 ... || `0x7ff0`
> +||mtimecmp for hart 4094|mtimecmp low for hart 4094 `0x7ff4`
> ||mtimecmp
> +|high for hart 4094 =======
> +
> +The Machine mode timer counter (`mtime`) is located at offset 0x7ff8 from
> the base address of operation parameters.
> +
> +.Registers layout of mtime
> +[width="60%",cols="1,^3,^3"]
> +|=======
> +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
> +|`0x7ff8` |mtime|mtime low `0x7ffc` ||mtime high =======
> +
>  // acknowledge all of the contributors
>  include::contributors.adoc[]
> --
> 2.19.0.windows.1
>
>
>
>
>


Re: [PATCH v5 0/2] System Peripherals

Mayuresh Chitale
 

Thanks Jonathan.


On Sat, May 22, 2021 at 11:16 PM Jonathan Behrens <behrensj@...> wrote:
This all looks good to me now.

Reviewed-by: Jonathan Behrens <behrensj@...>


On Fri, May 21, 2021 at 4:41 AM Mayuresh Chitale via lists.riscv.org <mchitale=ventanamicro.com@...> wrote:
This patch describes requirements for the system peripherals
like UART, clock and timers for the Linux-2022 platform
base spec and the server extension.

Changes in V5:
  - Rebased on main

Changes in V4:
  - Rephrased the requirement for minimum counter resolution

Changes in V3:

Base spec:
  - Clarified minimum requirement for counter resolution.

Server extension:
  - Removed watchdog timers section which to be moved into a separate patch.

Changes in V2:

Rephrased the requirements to use 'required' keyword instead of 'shall'.

Base spec:
  UART:
    - Added 8250 as deprecated and 16550 as mandatory

  Clock and Timers:
    - Move time csr, sstc requirement to server extension

Server extension:
  - Added Clock and Timers requirements
  - Added implementation notes for clock and watchdog timers

Changes in V1:
 - Initial draft for base spec only.

Mayuresh Chitale (2):
  Updating contributors
  System Peripherals: Linux 2022 Base spec and server extension

 contributors.adoc        |  3 ++-
 riscv-platform-spec.adoc | 43 +++++++++++++++++++++++++++++++++++++---
 2 files changed, 42 insertions(+), 4 deletions(-)

--
2.17.1







Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Anup Patel
 

-----Original Message-----
From: tech-unixplatformspec@... <tech-
unixplatformspec@...> On Behalf Of Abner Chang
Sent: 24 May 2021 08:34
To: tech-unixplatformspec@...
Cc: Alistair Francis <Alistair.Francis@...>; Sunil V L
<sunilvl@...>; Mayuresh Chitale
<mchitale@...>
Subject: [RISC-V] [tech-unixplatformspec] [PATCH v4 1/2] riscv-platform-spec:
PLIC and CLINT for Linux-2022 platform

From: Abner Chang <renba.chang@...>

Initial description of PLIC CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the platform
spec?

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't mention
IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not mandatory.
- Separate section in appendix for the Machine mode timer registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System Peripherals.
Do you think this is a good place for Machine Mode Timer?
@Mayuresh, please check if you are ok with this change, not sure if this
overlaps with your text or not (The timer setion). I can remove this
if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
section and CLINT in Linux-2022 Platform.
@Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------------
1 file changed, 62 insertions(+), 42 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index
160c74a..f8838ab 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,15 +49,37 @@ include::profiles.adoc[]
* Start Address

==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to
+route the non-local interrupts to the external interrupt of a hart
+context with a given privilege mode in a given hart. The number of
+non-local interrupt sources supported by PLIC and how does each of them
+connect to the hart context is PLIC core implementation-specific. +
+(Refer to
+https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RI
+SC-V PLIC Specification] for the implementation reference of PLIC
+operation parameters)
+
+===== CLINT[[CLINT]]
+On the contrast to PLIC, the Core Local Interrupt (CLINT) provides
+facilities to trigger local interrupt of <<MachineModeTimer,Machine mode
timer>> to hart.
We don't need a CLINT chapter in platform specification anymore.

Instead, we are proposing an Advanced CLINT (or ACLINT) which is:
1) Backward compatible with SiFive CLINT hence existing systems
will be compliant with new ACLINT spec
2) More modular compared to original CLINT and each functionality
is defined as a distinct device
3) Provision for S-mode software interrupts
4) Allow multi-socket (or mult-die) systems with multiple MTIMER,
MSWI, and SSWI devices defined by ACLINT spec.

The ACLINT helps us complete the IPI and Timer story for BASE
and Server platforms. Also, being backward compatible with SiFive
CLINT we don't need to point to define CLINT in platform spec.

The latest proposal of ACLINT spec is at:
https://github.com/avpatel/riscv-aclint-doc/blob/master/riscv-aclint.adoc

The ACLINT proposal was discussed in past platform meeting and
past AIA meeting as well.

Eventually, the ACLINT spec will be owned by RISC-V international
and hosted on RISC-V Github.

@Andrew Waterman can you please review ACLINT proposal ?

Regards,
Anup

+
+===== Interrupt Assignments

==== System Peripherals
-* UART/Serial Console
-* Clocks
-* Timers
-* Watchdog Timers
+===== UART/Serial Console
+===== Clocks
+===== Timers
+
+===== Machine Mode Timer[[MachineModeTimer]] Machine mode timer is
+required for Linux-2022 platform and incorporate with <<CLINT,CLINT>>
+to trigger the timer event to hart. The format of Machine mode timer
+operation parameters (`mtime` and `mtimecmp` registers) must compliant
with RISC-V Privilege specification section 3.1.10.
+The base address of the memory map registers of Machine mode timer is
+platform implementation-specific, however the offset of `mtime` and
+`mtimecmp` registers are fixed as <<machineModeTimerRegs,Machine mode
timer registers>>.
+
+
+===== Watchdog Timers

==== Boot Process
* Firmware
@@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022 specification.

==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant -
https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant -
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>,
+a spec compliant
+https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLI
+C]
or both a CLIC and and PLIC.

If using just a PLIC the system must continue to use the original basic @@ -
303,38 +324,9 @@ must be supported.
Embedded systems cannot use a non-compliant interrupt controller and still
call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must be -
implemented. The two registers must be memory mapped as required by the
RISC-V -specification.
-
-The Embedded-2022 specification requires that the registers be mapped -
adjacent to each other with the `mtime` region at the lower address.
-
-The starting address of this region can be located anywhere in -memory,
including inside other peripherals, as long as the start address is
-4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single hart is
below
-
--------------------------
-=========================
-| 0x00 | mtime low |
-| 0x04 | mtime high |
-| 0x08 | mtimecmp low |
-| 0x0C | mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 | mtime |
-| 0x08 | mtimecmp hart 1 |
-| 0x10 | mtimecmp hart 2 |
-===========================
----------------------------
+==== Machine Mode Timer
+The Embedded-2022 specification requires RISC-V
<<MachineModeTimer,Machine mode timer>> to be implemented.
+The Machine mode timer could be incorporated with the Core Local
Interrupt (<<CLINT, CLINT>>) or the specific event trigger mechanism
according to the platform design.

==== Memory Map
It is recommended that main memory and loadable code (not ROM) start at
@@ -349,5 +341,33 @@ When PMP is supported it is recommended to
include at least 4 regions, although if possible more should be supported to
allow more flexibility. Hardware implementations should aim for supporting
at least 16 PMP regions.

+// Appendix sections
+== Appendix
+=== Machine Mode Timer Registers [[MachineModeTimerRegs]] The base
+address of Machine mode timer operation parameters is platform
implementation-specific. The Machine mode timer compare registers
(`mtimecmp`) for each hart is located at offset 0 and the layout is organized
as below table.
+
+.Registers layout of mtimecmp
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
+|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0 `0x0004`
+|||mtimecmp high for hart 0 `0x0008` |mtimecmp for hart 1 |mtimecmp
low
+|for hart 1 `0x000c` ||mtimecmp high for hart 1 ... || `0x7ff0`
+||mtimecmp for hart 4094|mtimecmp low for hart 4094 `0x7ff4`
||mtimecmp
+|high for hart 4094 =======
+
+The Machine mode timer counter (`mtime`) is located at offset 0x7ff8 from
the base address of operation parameters.
+
+.Registers layout of mtime
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
+|`0x7ff8` |mtime|mtime low `0x7ffc` ||mtime high =======
+
// acknowledge all of the contributors
include::contributors.adoc[]
--
2.19.0.windows.1





Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Alistair Francis
 

On Mon, 2021-05-24 at 14:52 +0800, Abner Chang wrote:


Alistair Francis <Alistair.Francis@...> 於 2021年5月24日 週一
上午11:42寫道:
On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022
platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
mention
  IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not
mandatory.
- Separate section in appendix for the Machine mode timer
registers

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System
Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not
sure
if
this
  overlaps with your text or not (The timer setion). I can remove
this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System
Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt
Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
--
--
--
 1 file changed, 62 insertions(+), 42 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..f8838ab 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,15 +49,37 @@ include::profiles.adoc[]
 * Start Address
 
 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA[[AIA]]
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides
facilities
to route
+the non-local interrupts to the external interrupt of a hart
context
+with a given privilege mode in a given hart. The number of non-
local
interrupt
+sources supported by PLIC and how does each of them connect to
the
hart
+context is PLIC core implementation-specific. +
+(Refer to   
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
 PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== CLINT[[CLINT]]
+On the contrast to PLIC, the Core Local Interrupt (CLINT)
provides
I don't think this is a contrast to the PLIC, it's just a different
functionality.
Can rephase it. 

I'm also not sure the CLINT should be in the interrupt controller
section. It is the Core Local INTerruptor (CLINT), not an interrupt
controller.
Hmm.. CLINT is not a sort of interrupt controller but seems to me it
is unnecessary to create another section apart from the Interrupt
Controller section.
It probably makes more sense to add a timer section and put the CLNIT
there instead of forcing it into the interrupt controller section, when
it isn't really an interrupt controller.


+facilities to trigger local interrupt of
<<MachineModeTimer,Machine
mode timer>> to hart.
+
+===== Interrupt Assignments
 
 ==== System Peripherals
-* UART/Serial Console
-* Clocks
-* Timers
-* Watchdog Timers
+===== UART/Serial Console
+===== Clocks
+===== Timers
+
+===== Machine Mode Timer[[MachineModeTimer]]
+Machine mode timer is required for Linux-2022 platform and
incorporate with
+<<CLINT,CLINT>> to trigger the timer event to hart. The format
of
Machine mode timer operation parameters
+(`mtime` and `mtimecmp` registers) must compliant with RISC-V
s/must compliant/must be compliant/g
will correct this 

Privilege specification section 3.1.10.
+The base address of the memory map registers of Machine mode
timer
is platform implementation-specific,
+however the offset of `mtime` and `mtimecmp` registers are fixed
as
+<<machineModeTimerRegs,Machine mode timer registers>>.
+
+
+===== Watchdog Timers
 
 ==== Boot Process
 * Firmware
@@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
can
meet the Embedded-2022
 specification.
 
 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-       
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant
<<PLIC,PLIC>>, a spec
+compliant         
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.
 
 If using just a PLIC the system must continue to use the
original
basic
@@ -303,38 +324,9 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller
and
still
 call it a PLIC or CLIC.
 
-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
must be
-implemented. The two registers must be memory mapped as required
by
the RISC-V
-specification.
-
-The Embedded-2022 specification requires that the registers be
mapped
-adjacent to each other with the `mtime` region at the lower
address.
-
-The starting address of this region can be located anywhere in
-memory, including inside other peripherals, as long as the start
address is
-4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a
single
hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
----------------------------
+==== Machine Mode Timer
+The Embedded-2022 specification requires RISC-V
<<MachineModeTimer,Machine mode timer>> to be implemented.
+The Machine mode timer could be incorporated with the Core Local
Interrupt (<<CLINT, CLINT>>) or the specific event trigger
mechanism

CLINT is INTerruptor not just Interrupt.
yes, will correct it

according to the platform design.
What specific trigger mechanism?
platform implementation-specific trigger mechanism?  or just remove
I meant you didn't say what the mechanism is. It should be explicit, so
that there are no ambiguities.

this? I put this just because the previous feedback says a small
system may not have CLINT for the m-mode timer.
I would be in favour of saying either do what we already have written
here OR a CLINT.

If we go with something else that's ok, we just need to be clear about
what it is.


 
 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM)
start
at
@@ -349,5 +341,33 @@ When PMP is supported it is recommended to
include at least 4 regions, although
 if possible more should be supported to allow more flexibility.
Hardware
 implementations should aim for supporting at least 16 PMP
regions.
 
+// Appendix sections
+== Appendix
+=== Machine Mode Timer Registers [[MachineModeTimerRegs]]
+The base address of Machine mode timer operation parameters is
platform implementation-specific. The Machine mode timer compare
registers (`mtimecmp`) for each hart is located at offset 0 and
the
layout is organized as below table.
Can we maintain what we have for the embedded spec?
Do you mean to maintain the register layout(offset) originally
defined in the 2.2.3. for embedded systems? 
Yes. I worry that mandating a CLINT layout is too restrictive and that
no one will end up following the embedded-2022 spec then. I would be in
favour of saying CLINT or the memory layout we already have.

I think we have the register layout as below to be compliant with the
m-mode timer registers defined in SiFive CLINT.
I don't think that's flexible enough and that vendors won't want to
follow it as they already have other IP they are using for timers.

Alistair

Or do you mean something else?

 It allows the
memory maps to be inside of a MMIO device. For example they can be
registers inside of a general system controller.


Also it looks like the lines are a little long here, can be bring
them
back to 80 charecters?
sure. 

+
+.Registers layout of mtimecmp
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
RV32*
+|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
+|`0x0004` ||mtimecmp high for hart 0
+|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
+|`0x000c` ||mtimecmp high for hart 1
+|... ||
+|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
+|`0x7ff4` ||mtimecmp high for hart 4094
+|=======
+
+The Machine mode timer counter (`mtime`) is located at offset
0x7ff8
from the base address of operation parameters.
+
+.Registers layout of mtime
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
RV32*
+|`0x7ff8` |mtime|mtime low
+|`0x7ffc` ||mtime high
+|=======
Are you saying for a small embedded single core CPU we need to put
mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
addresses between them?

Alistair

+
 // acknowledge all of the contributors
 include::contributors.adoc[]


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Abner Chang
 



Alistair Francis <Alistair.Francis@...> 於 2021年5月24日 週一 上午11:42寫道:
On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> From: Abner Chang <renba.chang@...>
>
> Initial description of PLIC  CLINT section of Linux-2022 platform.
>
> Is this what we want to see of CLINT/Machine mode timer in the
> platform spec?
>
> On v4 commit,
> - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> mention
>   IPI because AIA already supported it.
> - In Embedded-2022 Machine mode timer section, CLINT is not
> mandatory.
> - Separate section in appendix for the Machine mode timer registers
>
> On v3 commit,
> - Address review comments.
>
> On v2 commit,
> - CLINT is not deprecated.
>
> - Add a standalone section for Machine Mode Timer in System
> Peripherals.
>   Do you think this is a good place for Machine Mode Timer?
>   @Mayuresh, please check if you are ok with this change, not sure if
> this
>   overlaps with your text or not (The timer setion). I can remove
> this
>   if you prefer to put this with your patch.
>
> - In Embedded-2022, refer to Machine Mode Timer in System Peripherals
>   section and CLINT in Linux-2022 Platform.
>   @Alistair, is this ok?
>
> On v1 commit,
> - Not sure where to put the [DEPRECATED].
> - Change the reference of PLIC in section 2.2.2. Interrupt Controller
> to
>   1.1.3.2 PLIC + CLINT section.
>
> Signed-off-by: Abner Chang <renba.chang@...>
> Cc: Alistair Francis <alistair.francis@...>
> Cc: Sunil V L <sunilvl@...>
> Cc: Mayuresh Chitale <mchitale@...>
> ---
>  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++--------------
> --
>  1 file changed, 62 insertions(+), 42 deletions(-)
>
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> index 160c74a..f8838ab 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -49,15 +49,37 @@ include::profiles.adoc[]
>  * Start Address
>  
>  ==== Interrupt Controller
> -* AIA
> -* PLIC + CLINT
> -* Interrupt Assignments
> +===== AIA[[AIA]]
> +===== PLIC[DEPRECATED][[PLIC]]
> +The Platform Level Interrupt Controller (PLIC) provides facilities
> to route
> +the non-local interrupts to the external interrupt of a hart context
> +with a given privilege mode in a given hart. The number of non-local
> interrupt
> +sources supported by PLIC and how does each of them connect to the
> hart
> +context is PLIC core implementation-specific. +
> +(Refer to   
> https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
>  PLIC Specification]
> +for the implementation reference of PLIC operation parameters)
> +
> +===== CLINT[[CLINT]]
> +On the contrast to PLIC, the Core Local Interrupt (CLINT) provides

I don't think this is a contrast to the PLIC, it's just a different
functionality.
Can rephase it. 

I'm also not sure the CLINT should be in the interrupt controller
section. It is the Core Local INTerruptor (CLINT), not an interrupt
controller.
Hmm.. CLINT is not a sort of interrupt controller but seems to me it is unnecessary to create another section apart from the Interrupt Controller section.

> +facilities to trigger local interrupt of <<MachineModeTimer,Machine
> mode timer>> to hart.
> +
> +===== Interrupt Assignments
>  
>  ==== System Peripherals
> -* UART/Serial Console
> -* Clocks
> -* Timers
> -* Watchdog Timers
> +===== UART/Serial Console
> +===== Clocks
> +===== Timers
> +
> +===== Machine Mode Timer[[MachineModeTimer]]
> +Machine mode timer is required for Linux-2022 platform and
> incorporate with
> +<<CLINT,CLINT>> to trigger the timer event to hart. The format of
> Machine mode timer operation parameters
> +(`mtime` and `mtimecmp` registers) must compliant with RISC-V

s/must compliant/must be compliant/g
will correct this 

> Privilege specification section 3.1.10.
> +The base address of the memory map registers of Machine mode timer
> is platform implementation-specific,
> +however the offset of `mtime` and `mtimecmp` registers are fixed as
> +<<machineModeTimerRegs,Machine mode timer registers>>.
> +
> +
> +===== Watchdog Timers
>  
>  ==== Boot Process
>  * Firmware
> @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G can
> meet the Embedded-2022
>  specification.
>  
>  ==== Interrupt Controller
> -Embedded systems are recommended to use a spec compliant
> -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> -       
> https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> +Embedded systems are recommended to use a spec compliant
> <<PLIC,PLIC>>, a spec
> +compliant         
> https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
>  or both a CLIC and and PLIC.
>  
>  If using just a PLIC the system must continue to use the original
> basic
> @@ -303,38 +324,9 @@ must be supported.
>  Embedded systems cannot use a non-compliant interrupt controller and
> still
>  call it a PLIC or CLIC.
>  
> -==== Machine Timer
> -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> must be
> -implemented. The two registers must be memory mapped as required by
> the RISC-V
> -specification.
> -
> -The Embedded-2022 specification requires that the registers be
> mapped
> -adjacent to each other with the `mtime` region at the lower address.
> -
> -The starting address of this region can be located anywhere in
> -memory, including inside other peripherals, as long as the start
> address is
> -4 byte aligned.
> -
> -An example of the memory layout for a 32-bit system with a single
> hart is below
> -
> --------------------------
> -=========================
> -| 0x00 |  mtime low     |
> -| 0x04 |  mtime high    |
> -| 0x08 |  mtimecmp low  |
> -| 0x0C |  mtimecmp high |
> -=========================
> --------------------------
> -
> -and for a 64-bit system with 2 harts
> -
> ----------------------------
> -===========================
> -| 0x00 |  mtime           |
> -| 0x08 |  mtimecmp hart 1 |
> -| 0x10 |  mtimecmp hart 2 |
> -===========================
> ----------------------------
> +==== Machine Mode Timer
> +The Embedded-2022 specification requires RISC-V
> <<MachineModeTimer,Machine mode timer>> to be implemented.
> +The Machine mode timer could be incorporated with the Core Local
> Interrupt (<<CLINT, CLINT>>) or the specific event trigger mechanism

CLINT is INTerruptor not just Interrupt.
yes, will correct it

> according to the platform design.

What specific trigger mechanism?
platform implementation-specific trigger mechanism?  or just remove this? I put this just because the previous feedback says a small system may not have CLINT for the m-mode timer.

>  
>  ==== Memory Map
>  It is recommended that main memory and loadable code (not ROM) start
> at
> @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> include at least 4 regions, although
>  if possible more should be supported to allow more flexibility.
> Hardware
>  implementations should aim for supporting at least 16 PMP regions.
>  
> +// Appendix sections
> +== Appendix
> +=== Machine Mode Timer Registers [[MachineModeTimerRegs]]
> +The base address of Machine mode timer operation parameters is
> platform implementation-specific. The Machine mode timer compare
> registers (`mtimecmp`) for each hart is located at offset 0 and the
> layout is organized as below table.

Can we maintain what we have for the embedded spec?
Do you mean to maintain the register layout(offset) originally defined in the 2.2.3. for embedded systems? 
I think we have the register layout as below to be compliant with the m-mode timer registers defined in SiFive CLINT.
Or do you mean something else?

It allows the
memory maps to be inside of a MMIO device. For example they can be
registers inside of a general system controller.

Also it looks like the lines are a little long here, can be bring them
back to 80 charecters?
sure. 

> +
> +.Registers layout of mtimecmp
> +[width="60%",cols="1,^3,^3"]
> +|=======
> +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
> +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> +|`0x0004` ||mtimecmp high for hart 0
> +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> +|`0x000c` ||mtimecmp high for hart 1
> +|... ||
> +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> +|`0x7ff4` ||mtimecmp high for hart 4094
> +|=======
> +
> +The Machine mode timer counter (`mtime`) is located at offset 0x7ff8
> from the base address of operation parameters.
> +
> +.Registers layout of mtime
> +[width="60%",cols="1,^3,^3"]
> +|=======
> +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
> +|`0x7ff8` |mtime|mtime low
> +|`0x7ffc` ||mtime high
> +|=======

Are you saying for a small embedded single core CPU we need to put
mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
addresses between them?

Alistair

> +
>  // acknowledge all of the contributors
>  include::contributors.adoc[]


Re: [PATCH v4 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

Andrew Waterman
 



On Sun, May 23, 2021 at 9:33 PM Alistair Francis <Alistair.Francis@...> wrote:
On Sun, 2021-05-23 at 20:49 -0700, Andrew Waterman wrote:
>
>
> On Sun, May 23, 2021 at 8:42 PM Alistair Francis < 
> alistair.francis@...> wrote:
> > On Mon, 2021-05-24 at 11:03 +0800, Abner Chang wrote:
> > > From: Abner Chang <renba.chang@...>
> > >
> > > Initial description of PLIC  CLINT section of Linux-2022
> > > platform.
> > >
> > > Is this what we want to see of CLINT/Machine mode timer in the
> > > platform spec?
> > >
> > > On v4 commit,
> > > - PLIC section with [DEPRECATED] in Linux- 2022 chapter
> > > - CLINT section in Linux- 2022 chapter for M-mode timer. We don't
> > > mention
> > >   IPI because AIA already supported it.
> > > - In Embedded-2022 Machine mode timer section, CLINT is not
> > > mandatory.
> > > - Separate section in appendix for the Machine mode timer
> > > registers
> > >
> > > On v3 commit,
> > > - Address review comments.
> > >
> > > On v2 commit,
> > > - CLINT is not deprecated.
> > >
> > > - Add a standalone section for Machine Mode Timer in System
> > > Peripherals.
> > >   Do you think this is a good place for Machine Mode Timer?
> > >   @Mayuresh, please check if you are ok with this change, not
> > > sure
> > if
> > > this
> > >   overlaps with your text or not (The timer setion). I can remove
> > > this
> > >   if you prefer to put this with your patch.
> > >
> > > - In Embedded-2022, refer to Machine Mode Timer in System
> > Peripherals
> > >   section and CLINT in Linux-2022 Platform.
> > >   @Alistair, is this ok?
> > >
> > > On v1 commit,
> > > - Not sure where to put the [DEPRECATED].
> > > - Change the reference of PLIC in section 2.2.2. Interrupt
> > Controller
> > > to
> > >   1.1.3.2 PLIC + CLINT section.
> > >
> > > Signed-off-by: Abner Chang <renba.chang@...>
> > > Cc: Alistair Francis <alistair.francis@...>
> > > Cc: Sunil V L <sunilvl@...>
> > > Cc: Mayuresh Chitale <mchitale@...>
> > > ---
> > >  riscv-platform-spec.adoc | 104 +++++++++++++++++++++++----------
> > > --
> > --
> > > --
> > >  1 file changed, 62 insertions(+), 42 deletions(-)
> > >
> > > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > > index 160c74a..f8838ab 100644
> > > --- a/riscv-platform-spec.adoc
> > > +++ b/riscv-platform-spec.adoc
> > > @@ -49,15 +49,37 @@ include::profiles.adoc[]
> > >  * Start Address
> > >  
> > >  ==== Interrupt Controller
> > > -* AIA
> > > -* PLIC + CLINT
> > > -* Interrupt Assignments
> > > +===== AIA[[AIA]]
> > > +===== PLIC[DEPRECATED][[PLIC]]
> > > +The Platform Level Interrupt Controller (PLIC) provides
> > > facilities
> > > to route
> > > +the non-local interrupts to the external interrupt of a hart
> > context
> > > +with a given privilege mode in a given hart. The number of non-
> > local
> > > interrupt
> > > +sources supported by PLIC and how does each of them connect to
> > > the
> > > hart
> > > +context is PLIC core implementation-specific. +
> > > +(Refer to   
> > >
> > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
> > >  PLIC Specification]
> > > +for the implementation reference of PLIC operation parameters)
> > > +
> > > +===== CLINT[[CLINT]]
> > > +On the contrast to PLIC, the Core Local Interrupt (CLINT)
> > > provides
> >
> > I don't think this is a contrast to the PLIC, it's just a different
> > functionality.
> >
> > I'm also not sure the CLINT should be in the interrupt controller
> > section. It is the Core Local INTerruptor (CLINT), not an interrupt
> > controller.
> >
> > > +facilities to trigger local interrupt of
> > <<MachineModeTimer,Machine
> > > mode timer>> to hart.
> > > +
> > > +===== Interrupt Assignments
> > >  
> > >  ==== System Peripherals
> > > -* UART/Serial Console
> > > -* Clocks
> > > -* Timers
> > > -* Watchdog Timers
> > > +===== UART/Serial Console
> > > +===== Clocks
> > > +===== Timers
> > > +
> > > +===== Machine Mode Timer[[MachineModeTimer]]
> > > +Machine mode timer is required for Linux-2022 platform and
> > > incorporate with
> > > +<<CLINT,CLINT>> to trigger the timer event to hart. The format
> > > of
> > > Machine mode timer operation parameters
> > > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> >
> > s/must compliant/must be compliant/g
> >
> > > Privilege specification section 3.1.10.
> > > +The base address of the memory map registers of Machine mode
> > > timer
> > > is platform implementation-specific,
> > > +however the offset of `mtime` and `mtimecmp` registers are fixed
> > as
> > > +<<machineModeTimerRegs,Machine mode timer registers>>.
> > > +
> > > +
> > > +===== Watchdog Timers
> > >  
> > >  ==== Boot Process
> > >  * Firmware
> > > @@ -289,9 +311,8 @@ Any RISC-V system that uses at least RV32/64G
> > can
> > > meet the Embedded-2022
> > >  specification.
> > >  
> > >  ==== Interrupt Controller
> > > -Embedded systems are recommended to use a spec compliant
> > > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > > -       
> > >
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > > +Embedded systems are recommended to use a spec compliant
> > > <<PLIC,PLIC>>, a spec
> > > +compliant         
> > >
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > >  or both a CLIC and and PLIC.
> > >  
> > >  If using just a PLIC the system must continue to use the
> > > original
> > > basic
> > > @@ -303,38 +324,9 @@ must be supported.
> > >  Embedded systems cannot use a non-compliant interrupt controller
> > and
> > > still
> > >  call it a PLIC or CLIC.
> > >  
> > > -==== Machine Timer
> > > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > > must be
> > > -implemented. The two registers must be memory mapped as required
> > by
> > > the RISC-V
> > > -specification.
> > > -
> > > -The Embedded-2022 specification requires that the registers be
> > > mapped
> > > -adjacent to each other with the `mtime` region at the lower
> > address.
> > > -
> > > -The starting address of this region can be located anywhere in
> > > -memory, including inside other peripherals, as long as the start
> > > address is
> > > -4 byte aligned.
> > > -
> > > -An example of the memory layout for a 32-bit system with a
> > > single
> > > hart is below
> > > -
> > > --------------------------
> > > -=========================
> > > -| 0x00 |  mtime low     |
> > > -| 0x04 |  mtime high    |
> > > -| 0x08 |  mtimecmp low  |
> > > -| 0x0C |  mtimecmp high |
> > > -=========================
> > > --------------------------
> > > -
> > > -and for a 64-bit system with 2 harts
> > > -
> > > ----------------------------
> > > -===========================
> > > -| 0x00 |  mtime           |
> > > -| 0x08 |  mtimecmp hart 1 |
> > > -| 0x10 |  mtimecmp hart 2 |
> > > -===========================
> > > ----------------------------
> > > +==== Machine Mode Timer
> > > +The Embedded-2022 specification requires RISC-V
> > > <<MachineModeTimer,Machine mode timer>> to be implemented.
> > > +The Machine mode timer could be incorporated with the Core Local
> > > Interrupt (<<CLINT, CLINT>>) or the specific event trigger
> > mechanism
> >
> > CLINT is INTerruptor not just Interrupt.
> >
> > > according to the platform design.
> >
> > What specific trigger mechanism?
> >
> > >  
> > >  ==== Memory Map
> > >  It is recommended that main memory and loadable code (not ROM)
> > start
> > > at
> > > @@ -349,5 +341,33 @@ When PMP is supported it is recommended to
> > > include at least 4 regions, although
> > >  if possible more should be supported to allow more flexibility.
> > > Hardware
> > >  implementations should aim for supporting at least 16 PMP
> > > regions.
> > >  
> > > +// Appendix sections
> > > +== Appendix
> > > +=== Machine Mode Timer Registers [[MachineModeTimerRegs]]
> > > +The base address of Machine mode timer operation parameters is
> > > platform implementation-specific. The Machine mode timer compare
> > > registers (`mtimecmp`) for each hart is located at offset 0 and
> > > the
> > > layout is organized as below table.
> >
> > Can we maintain what we have for the embedded spec? It allows the
> > memory maps to be inside of a MMIO device. For example they can be
> > registers inside of a general system controller.
> >
> > Also it looks like the lines are a little long here, can be bring
> > them
> > back to 80 charecters?
> >
> > > +
> > > +.Registers layout of mtimecmp
> > > +[width="60%",cols="1,^3,^3"]
> > > +|=======
> > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > > +|`0x0000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > > +|`0x0004` ||mtimecmp high for hart 0
> > > +|`0x0008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > > +|`0x000c` ||mtimecmp high for hart 1
> > > +|... ||
> > > +|`0x7ff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > > +|`0x7ff4` ||mtimecmp high for hart 4094
> > > +|=======
> > > +
> > > +The Machine mode timer counter (`mtime`) is located at offset
> > 0x7ff8
> > > from the base address of operation parameters.
> > > +
> > > +.Registers layout of mtime
> > > +[width="60%",cols="1,^3,^3"]
> > > +|=======
> > > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > > +|`0x7ff8` |mtime|mtime low
> > > +|`0x7ffc` ||mtime high
> > > +|=======
> >
> > Are you saying for a small embedded single core CPU we need to put
> > mtimecmp at offset 0x00 and mtime at 0x7ff8? What about all the
> > addresses between them?
> >
>
>
> What you're hinting at is a false economy.  There really isn't any
> cost to having an empty two pages of address space, even in small,
> embedded single-core systems.

I agree, but if this is included inside a system controller (as mtime
and mtimecmp sometimes are) I'm worried that HW vendors will then just
put them next to each other to condense the address space and not meet
this spec. 

I have seen hardware vendors complain about changing address space
layouts in the past and I'm worried this large gap will be a reason not
to meet the spec. Considering there is already "RISC-V" hardware that
doesn't include mtime/mtimecmp I would like to make this spec as easy
as possible for vendors to meet, so that hopefully everyone does.

In saying that you know a lot more about HW design then me, so if you
think it won't be an issue then we can leave it as is.

People indeed do questionable things all the time.  But I can assure you, this one isn't going to materially affect HW cost, one way or the other.


Alistair

>
> >
> > Alistair
> >
> > > +
> > >  // acknowledge all of the contributors
> > >  include::contributors.adoc[]
> >
> >
> >
> >
> >
> >

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