Add requirement for preserving the PCIe ID routing as described in issue: https://github.com/riscv/riscv-platform-specs/issues/81 Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-

As discussed on the mailing list: - 4.7.3.4 - Fixed typo - Added clarification for requests with NS=1, RO=0 - 4.7.3.5 - Added topology depicting a RP, RCiEP, RCEC on the root bus - Removed constraint

Agreed ! I will send a patch for this change. Ok. Will do that.

The intention behind requiring intx was to ensure better compatibility. There are few cases where we fallback to INTx if MSI is not available. For e.g: https://elixir.bootlin.com/linux/v5.15.12/source

This patch adds requirements for mapping PCIe interrupts to AIA. Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 23 +++++++++++++++++++++-- 1 file changed, 2

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- Makefile | 18 +++-- pcie-topology.ditaa | 28 ++++++++ riscv-platf

V5: - Improve text for PCIe cache coherency requirement. V4: - Fix Pcie cache coherency requirement to use 'No_Snoop bit' instead of 'No_snoop' - Removed empty section for peer-to-peer transactions V3

Thanks Atish. Actually one more revision is required for this patch. During an internal review, a modification was suggested to me for the PCIe cache coherency requirement text. I will do that and sen

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- Makefile | 18 +++-- pcie-topology.ditaa | 28 ++++++++ riscv-platf

V4: - Fix Pcie cache coherency requirement to use 'No_Snoop bit' instead of 'No_snoop' - Removed empty section for peer-to-peer transactions V3: - Replaced references to PMA+PBMT by PMA - Moved the PC

Yes, I think this is reasonable.

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- Makefile | 18 +++-- pcie-topology.ditaa | 28 ++++++++ riscv-platf

V3: - Replaced references to PMA+PBMT by PMA - Moved the PCIe topology diagram to a separate adoc to enable it's inclusion into PDF V2: - Fixed abbreviation for root complex integrated endpoint - Adde

No, actually it just means that if the watchdog timer is never refreshed after the first stage timeout then a second stage timeout would occur. The mechanism to configure the timeout value is not spec

Actually it is present in the 'Required ACPI System Description Tables'. I can add a pointer to that table in the text above. I will rephrase all instances of this as Greg mentioned in his latest emai

This patch describes requirements for the watchdog timer for the server extension. Signed-off-by: Greg Favor <gfavor@...> Signed-off-by: Mayuresh Chitale <mchitale@...> --- r

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 174 ++++++++++++++++++++++++++++++++++

V2: - Fixed abbreviation for root complex integrated endpoint - Added section for PCIe device firmware requirement. V1: - Initial patch. Mayuresh Chitale (1): server extension: PCIe requirements riscv

Sure. Yes, I will fix in the next revision. Yes, looks like I missed it. I will include it in the next revision.

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 166 ++++++++++++++++++++++++++++++++++