Got it. I understand what you are saying now and agree. regards ved

I think of UD being orthogonal to this discussion. Firmware world | OS world | [UD, etc. ]---firmware builds-+->[ACPI/DT]--->OS | | So the comments about early boot etc. in this thread I read as refer

Sunil Hi - July 4 is a holiday in the US. COuld we meet on 5th? regards ved

I get the intent now. But we may not want to prohibit that. We may want to document that the SBI will access this memory using the PMA attribute. If the supervisor has accessed this same location usin

So domain is a new term which is not presently defined in the privileged specification or in the SBI specification. I think I get what you may be stating here i.e., M-mode may configure/ reconfigure P

I think the extension was proposed to be a Debug console extension. In a production environment if 10's of VMs were booting having them emit to the physical console - where all of those outputs will g

Of course a console is needed. But I was questioning the need for something much more elaborate than a putchar/getchar interface. I understand its needed to port the hypervisor but I undersatnd it wou

Since this is for debug and really early phase debug till enough of the guest boots up to use a VFIO based char driver provided by the VMM, I am not sure that the slowness matters. Even this SBI call

Should we keep this simple in the SBI - only have register based inputs - to send and receive 1 byte in each call? Keeping it a simple out_byte or in_byte - a serial port like interface seems the simp

Are there downsides to the debugger inhibiting the timer interrupt by setting STIE to 0? This seems like would provide similar benefit even for a multi-hart system... regards ved

Greg HI I agree architecturally there is just memory-mapped MTIME. We can leave it at that. What I meant by clock was where a each hart has its unique memory mapped MTIME and thereby is clocked by a r

So there is an assumption here that somehow time is broadcast and not the clock. For an implementation that does clock broadcast this requirement requires having a shadow time that counts while softwa

Greg HI - Thanks. I think this is very clear. I think the recommendation could be changed to require MSI and make supporting INTx emulation optional. I am hoping to hear from BIOS and OS experts if we

So we could drop these statements: " - Main memory must be protected with SECDED-ECC. - All cache structures must be protected. - single-bit errors must be detected and corrected. - multi-bit errors c

I agree. I think the RAS ISA would want to be about standardized error logging and reporting but not mandate what errors are detected/corrected and how they are corrected or contained. For example, ev

Totally agree that the term "cache structure" is ambigous and variety of caches may be built. How caches are built should also be transparent to the ISA, software, and the platform in general. Like yo

Will be glad to. Yes, that sounds good. regards ved

Thanks. Yes. Could I suggest: "Cache structures must be protected to address the Failure-in-time (FIT) requirements. The protection mechanisms may included single-bit/multi-bit error detection and/or

Hi Anup Yes, that was my conclusion that "software interrupt" here was used to mean an IPI. I think clearing this up would be helpful. Yes, however the Server is additived to the base as written. Even

I was thinking along the lines of how Greg was thinking here. Agree. Agree. regards ved