[PATCH v3 0/4] riscv: Add qspinlock/qrwlock


From: Guo Ren <guoren@...>

Current riscv is still using baby spinlock implementation. It'll cause
fairness and cache line bouncing problems. Many people are involved
and pay the efforts to improve it:

- The first version of patch was made in 2019.1:

- The second version was made in 2020.11:

- A good discussion at Platform HSC.2021-03-08:

Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...

Let's kick the qspinlock into riscv right now (Also for the
architectures which doesn't have short atmoic xchg instructions.)

Change V3:
- Fixup short-xchg asm code (slli -> slliw, srli -> srliw)
- Coding convention by Peter Zijlstra's advices

Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations

V1: (by michael)

Guo Ren (3):
riscv: cmpxchg.h: Cleanup unused code
riscv: cmpxchg.h: Merge macros
riscv: cmpxchg.h: Implement xchg for short

Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

arch/riscv/Kconfig | 2 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/cmpxchg.h | 211 ++++++------------------
arch/riscv/include/asm/spinlock.h | 126 +-------------
arch/riscv/include/asm/spinlock_types.h | 15 +-
5 files changed, 58 insertions(+), 299 deletions(-)