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[PATCH v6 1/2] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform
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Alistair Francis <alistair.francis@...>
On Sat, 2021-05-29 at 22:42 +0800, renba.chang@... wrote:
From: Abner Chang <renba.chang@...>Acked-by: Alistair Francis <alistair.francis@...> Alistair --- |
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atishp@...
On Mon, 2021-06-07 at 22:56 +0800, Abner Chang wrote:
Yes. I think it was not reviewed in the past. At least that's what I remember. If I am wrong about that, it's fine. --Yes, it's fair. Regards, Atish |
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Atish Patra <Atish.Patra@...> 於 2021年6月5日 週六 上午3:14寫道： On Sat, 2021-05-29 at 22:42 +0800, Abner Chang wrote: Hi Atish, Do you mean to send the patch of PLIC spec on https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc?
Yes, it's fair. Abner
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atishp@...
On Sat, 2021-05-29 at 22:42 +0800, Abner Chang wrote:
From: Abner Chang <renba.chang@...>IIRC, PLIC spec was never reviewed widely. As this group is more active now, tt would be good to send it as a separate patch so we can do a detailed review of that as well. I am just concerned about semantics rather than technical details. +for the implementation reference of PLIC operation parameters)We have now official names for the PLATFORM spec. We should refer to that. requires the Advanced Core Local Interruptor (ACLINT, +===== Interrupt Assignments-- Regards, Atish |
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From: Abner Chang <renba.chang@...>
Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove CLINT from platform spec - Require ACLINT on Linux2020 platform and have a link to https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc. - Remove Machine mode timer from previous patch because that is in the scope of ACLINT - For Embedded-2022 platform, mention Machine mode timer and refer to ACLINT for the definition of registers On v4 commit, - PLIC section with [DEPRECATED] in Linux- 2022 chapter - CLINT section in Linux- 2022 chapter for M-mode timer. We don't mention IPI because AIA already supported it. - In Embedded-2022 Machine mode timer section, CLINT is not mandatory. - Separate section in appendix for the Machine mode timer registers On v3 commit, - Address review comments. On v2 commit, - CLINT is not deprecated. - Add a standalone section for Machine Mode Timer in System Peripherals. Do you think this is a good place for Machine Mode Timer? @Mayuresh, please check if you are ok with this change, not sure if this overlaps with your text or not (The timer setion). I can remove this if you prefer to put this with your patch. - In Embedded-2022, refer to Machine Mode Timer in System Peripherals section and CLINT in Linux-2022 Platform. @Alistair, is this ok? On v1 commit, - Not sure where to put the [DEPRECATED]. - Change the reference of PLIC in section 2.2.2. Interrupt Controller to 1.1.3.2 PLIC + CLINT section. Signed-off-by: Abner Chang <renba.chang@...> Cc: Alistair Francis <alistair.francis@...> Cc: Sunil V L <sunilvl@...> Cc: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index 160c74a..c0ee75d 100644 --- a/riscv-platform-spec.adoc +++ b/riscv-platform-spec.adoc @@ -49,9 +49,24 @@ include::profiles.adoc[] * Start Address ==== Interrupt Controller -* AIA -* PLIC + CLINT -* Interrupt Assignments +===== AIA[[AIA]] +===== PLIC[DEPRECATED][[PLIC]] +The Platform Level Interrupt Controller (PLIC) provides facilities to route +the non-local interrupts to the external interrupt of a hart context +with a given privilege mode in a given hart. The number of non-local interrupt +sources supported by PLIC and how does each of them connect to the hart +context is PLIC core implementation-specific. + +(Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification] +for the implementation reference of PLIC operation parameters) + +===== ACLINT +Linux-2020 platform requires the Advanced Core Local Interruptor (ACLINT, +refer to +https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc[RISC-V ACLINT Specification]) +to provide facilities to route inter-processor interrupt and Machine mode timer +interrupt to each RISC-V processor hart. + +===== Interrupt Assignments ==== System Peripherals * UART/Serial Console @@ -289,8 +304,8 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022 specification. ==== Interrupt Controller -Embedded systems are recommended to use a spec compliant -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant +Embedded systems are recommended to use a spec compliant <<PLIC,PLIC>>, +a spec compliant https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC] or both a CLIC and and PLIC. -- 2.19.0.windows.1 |
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