Please see inline below ....

Regards,
Anup

On 28/07/21, 11:30 PM, "Heinrich Schuchardt" <xypron.glpk@...> wrote:



On 28.07.21 15:33, Anup Patel wrote:
> To have a meaningful H-extension support, both OS/A-base and
> OS/A-server platforms must comply with additional requirements
> for H-extension.
>
> Signed-off-by: Anup Patel <anup.patel@...>
> ---
> riscv-platform-spec.adoc | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> index a24281f..ce34768 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -120,6 +120,12 @@ The M platform has the following extensions:
> values.)
> ** Platforms is allowed to operate only in little-endian mode i.e.
> implementations must hardwire the mstatus.MBE field to 0.
> +** If H-extension is implemented then the OS-A platform must comply with

Just a few typos

%s/If H-extension/If the H-extension/

%s/with/with the/

> + following additional requirements:
> +*** Upon guest page faults taken into HS-mode, the `htval` CSR must provide
> + the guest physcial address right shifted by 2.

%s/pyscial/physical/

> +*** Upon guest page faults taken into M-mode, the `mtval2` CSR must provide
> + the guest physcial address right shifted by 2.

Ditto

[Anup] Thanks, I will address your comments in v2

Best regards

Heinrich

>
> [sidebar]
> --
> @@ -448,9 +454,13 @@ base with the additional requirements as below.
> ==== Architecture
> The platforms which conform to server extension are required to implement +
>
> -- RV64 support
> -- RISC-V H ISA extension
> -- VMID support
> +* RV64 support
> +* RISC-V ISA H-extension with following additional requirements:
> +** VMID support
> +** Upon load/store/AMO exceptions taken into HS-mode, the `htinst` CSR must
> + provide transformed standard instruction.
> +** Upon load/store/AMO exceptions taken into M-mode, the `mtinst` CSR must
> + provide transformed standard instruction.
>
> ==== PMU
>
>

On 28.07.21 15:33, Anup Patel wrote:

To have a meaningful H-extension support, both OS/A-base and
OS/A-server platforms must comply with additional requirements
for H-extension.

Signed-off-by: Anup Patel <anup.patel@...>
---
riscv-platform-spec.adoc | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index a24281f..ce34768 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -120,6 +120,12 @@ The M platform has the following extensions:
values.)
** Platforms is allowed to operate only in little-endian mode i.e.
implementations must hardwire the mstatus.MBE field to 0.
+** If H-extension is implemented then the OS-A platform must comply with

Just a few typos

%s/If H-extension/If the H-extension/

%s/with/with the/

+ following additional requirements:
+*** Upon guest page faults taken into HS-mode, the `htval` CSR must provide
+ the guest physcial address right shifted by 2.

%s/pyscial/physical/

+*** Upon guest page faults taken into M-mode, the `mtval2` CSR must provide
+ the guest physcial address right shifted by 2.

ditto

Best regards

Heinrich

[sidebar]
--
@@ -448,9 +454,13 @@ base with the additional requirements as below.
==== Architecture
The platforms which conform to server extension are required to implement +

-- RV64 support
-- RISC-V H ISA extension
-- VMID support
+* RV64 support
+* RISC-V ISA H-extension with following additional requirements:
+** VMID support
+** Upon load/store/AMO exceptions taken into HS-mode, the `htinst` CSR must
+ provide transformed standard instruction.
+** Upon load/store/AMO exceptions taken into M-mode, the `mtinst` CSR must
+ provide transformed standard instruction.

==== PMU

To have a meaningful H-extension support, both OS/A-base and
OS/A-server platforms must comply with additional requirements
for H-extension.

Signed-off-by: Anup Patel <anup.patel@...>
---
riscv-platform-spec.adoc | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index a24281f..ce34768 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -120,6 +120,12 @@ The M platform has the following extensions:
values.)
** Platforms is allowed to operate only in little-endian mode i.e.
implementations must hardwire the mstatus.MBE field to 0.
+** If H-extension is implemented then the OS-A platform must comply with
+ following additional requirements:
+*** Upon guest page faults taken into HS-mode, the `htval` CSR must provide
+ the guest physcial address right shifted by 2.
+*** Upon guest page faults taken into M-mode, the `mtval2` CSR must provide
+ the guest physcial address right shifted by 2.

[sidebar]
--
@@ -448,9 +454,13 @@ base with the additional requirements as below.
==== Architecture
The platforms which conform to server extension are required to implement +

-- RV64 support
-- RISC-V H ISA extension
-- VMID support
+* RV64 support
+* RISC-V ISA H-extension with following additional requirements:
+** VMID support
+** Upon load/store/AMO exceptions taken into HS-mode, the `htinst` CSR must
+ provide transformed standard instruction.
+** Upon load/store/AMO exceptions taken into M-mode, the `mtinst` CSR must
+ provide transformed standard instruction.

==== PMU

--
2.25.1