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[PATCH 1/6] Remove the machine mode requirements
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atishp@...
As per the discussion in the mailing list, M-mode requirements
should not be included in this version of the platform specification to allow platform vendors more flexibility in implementing privilege modes. Moreover, platform specification doesn't guarantee inter-operability between M-mode software/firmwares. Thus, specifying M-mode requirements adds restriction while not providing any significant value. Remove the machine mode requirements for this version of the platform specification. Signed-off-by: Atish Patra <atishp@...> --- riscv-platform-spec.adoc | 57 +++------------------------------------- 1 file changed, 4 insertions(+), 53 deletions(-) diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index b2388dbaf834..e20703299937 100644 --- a/riscv-platform-spec.adoc +++ b/riscv-platform-spec.adoc @@ -37,7 +37,6 @@ toc::[] |OSPM | Operating System Power Management |RVA22U64 | RISC-V 2022 user-mode profile <<spec_profiles>> |RVA22S64 | RISC-V 2022 supervisor-mode profile <<spec_profiles>> -|RVA22M64 | RISC-V 2022 machine-mode profile <<spec_profiles>> |RAS | Reliability, Availability, and Serviceability |CLINT | Legacy Core-Local Interrupt Controller |ACLINT | Advanced Core-Local Interrupt Controller <<spec_aclint>> @@ -98,6 +97,10 @@ feature set and extensions as shown below: + ** *Base* ** *Physical Memory Protection (PMP) Extension* +The current version of this platform spec targets the standardization of +functionality available in S, U, VS and VU modes, and the standardization of +the SBI (Supervisory Binary Interface as defined in <<spec_sbi>>) between +Supervisor level (S-mode/VS-mode) and M-mode/HS-mode respectively. // OS-A Platform == OS-A Platform @@ -111,7 +114,6 @@ feature set and extensions as shown below: + RISC-V profiles specification <<spec_profiles>>. ** RVA22U profile for user-mode. ** RVA22S profile for supervisor-mode. -** RVM20M64 profile for machine-mode. *** The I, M, A, C extensions must be supported. ===== General @@ -143,48 +145,6 @@ to all hart-related caches. User-mode programs should not execute the `fence.i` instruction. -- -===== Machine Mode -* mvendorid, marchid, mimpid and mhartid registers must be supported and not -hardwired to 0. - -* mstatus -** TVM bit must not be hardwired to 0. -** TW bit must not be hardwired to 0. -** TSR bit must not be hardwired to 0. -** MBE, SBE and UBE must each be either hardwired to 0 or writable and -initialized by reset or boot firmware for LE operation. - -* mtvec -** Both direct and vectored modes must be supported. -** The alignment constraint for BASE fields must be at most 256B. - -* medeleg -** All bits for defined and supported exceptions except 'Environment call -from M-mode' must be writable. - -* mideleg -** Bits for MSI, MTI and MEI must be hardwired to 0. - -* mcounteren -** Writeable bits must be implemented for all supported (not hardwired to zero) -hpmcounters. - -* mcountinhibit -** Writeable bits must be implemented for all supported (not hardwired to zero) -hpmcounters. - -* mtval -** mtval must not be hardwired to 0 and in all cases must be written with -non-zero and zero values as architecturally defined. - -* mtval2 -** If H extension is supported then mtval2 must not be hardwired to 0 and in -all cases must be written with non-zero and zero values as architecturally -defined. - -* PMP -** Minimum of 4 PMP regions must be supported. - ===== Supervisor mode * sstatus ** sstatus.UBE must support the same access attribute (read-only or writable) @@ -554,11 +514,6 @@ information population <<spec_unified_discovery>>. ** SBI HSM ** SBI SRST ** SBI PMU -* Required features of the M-Mode runtime also include: -** Delegate interrupts and exceptions to S-mode. -** Handle misaligned load and store. -** Emulate missing CSRs. -** Configure PMP CSRs. ===== UEFI @@ -603,10 +558,6 @@ satisfying a requirement. There should be hardware support for all misaligned accesses; misaligned accesses should not take address misaligned exceptions. -===== Machine Mode -* PMP/ePMP -** Minimum of 16 PMP regions must be supported. - ===== Supervisor mode * satp ** For RV64, Sv48 translation mode must be supported. -- 2.33.1 |
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Darius Rad
On Thu, Nov 18, 2021 at 04:09:28PM -0800, atishp@... wrote:
As per the discussion in the mailing list, M-mode requirementsStill doesn't provide standardization of functionality in U and VU modes. https://lists.riscv.org/g/tech-unixplatformspec/message/1479
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