[PATCH] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform


Abner Chang
 

From: Abner Chang <renba.chang@...>

Initial description of PLIC + CLINT section of Linux-2022 platform.

In this commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
---
riscv-platform-spec.adoc | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..f9179fb 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,19 @@ include::profiles.adoc[]
* Start Address

==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to route
+the non-local global interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local interrupt
+sources supported by PLIC and how does each of them connect to the hart context
+is PLIC core implementation-specific. Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]
+for the PLIC operation parameters details. On the contrast, the Core Local
+Interrupt (CLINT) provides the local interrupt mechanism for timer and software
+interrupt to the Machine mode of hart. The operation parameters of local interrupt
+is CLINT implementation-specific.
+
+===== Interrupt Assignments

==== System Peripherals
* UART/Serial Console
@@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
specification.

==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant <<PLICCLINT,PLIC>>, a spec compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
or both a CLIC and and PLIC.

--
2.19.0.windows.1


Alistair Francis
 

On Wed, 2021-05-05 at 12:30 +0800, Abner Chang wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC + CLINT section of Linux-2022 platform.

In this commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller
to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
---
 riscv-platform-spec.adoc | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..f9179fb 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,19 @@ include::profiles.adoc[]
 * Start Address
 
 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]
Is the CLINT also deprecated?

From what I can tell in the AIA spec it doesn't include a replacement
for the CLINT. What should be used for mtime/mtimecmp instead?

Alistair

+The Platform Level Interrupt Controller (PLIC) provides facilities
to route
+the non-local global interrupts to the external interrupt of a hart
context
+with a given privilege mode in a given hart. The number of non-local
interrupt
+sources supported by PLIC and how does each of them connect to the
hart context
+is PLIC core implementation-specific. Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
 PLIC Specification]
+for the PLIC operation parameters details. On the contrast, the Core
Local
+Interrupt (CLINT) provides the local interrupt mechanism for timer
and software
+interrupt to the Machine mode of hart. The operation parameters of
local interrupt
+is CLINT implementation-specific.
+
+===== Interrupt Assignments
 
 ==== System Peripherals
 * UART/Serial Console
@@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022
 specification.
 
 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant
<<PLICCLINT,PLIC>>, a spec compliant
 
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.


Abner Chang
 



Alistair Francis <Alistair.Francis@...> 於 2021年5月5日 週三 下午12:48寫道:
On Wed, 2021-05-05 at 12:30 +0800, Abner Chang wrote:
> From: Abner Chang <renba.chang@...>
>
> Initial description of PLIC + CLINT section of Linux-2022 platform.
>
> In this commit,
> - Not sure where to put the [DEPRECATED].
> - Change the reference of PLIC in section 2.2.2. Interrupt Controller
> to
>   1.1.3.2 PLIC + CLINT section.
>
> Signed-off-by: Abner Chang <renba.chang@...>
> Cc: Alistair Francis <alistair.francis@...>
> Cc: Sunil V L <sunilvl@...>
> ---
>  riscv-platform-spec.adoc | 19 ++++++++++++++-----
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> index 160c74a..f9179fb 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -49,9 +49,19 @@ include::profiles.adoc[]
>  * Start Address
>  
>  ==== Interrupt Controller
> -* AIA
> -* PLIC + CLINT
> -* Interrupt Assignments
> +===== AIA
> +===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]

Is the CLINT also deprecated?

From what I can tell in the AIA spec it doesn't include a replacement
for the CLINT. What should be used for mtime/mtimecmp instead?
Hmm, seems you are correct. AIA says it would expand the framework to local interrupts but RISC-V timer and software interrupt seem not involved.
Does AIA-IPI mechanism replace RISC-V software interrupt?
Can the task group clarify these questions?

Abner


Alistair

> +The Platform Level Interrupt Controller (PLIC) provides facilities
> to route
> +the non-local global interrupts to the external interrupt of a hart
> context
> +with a given privilege mode in a given hart. The number of non-local
> interrupt
> +sources supported by PLIC and how does each of them connect to the
> hart context
> +is PLIC core implementation-specific. Refer to
> https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
>  PLIC Specification]
> +for the PLIC operation parameters details. On the contrast, the Core
> Local
> +Interrupt (CLINT) provides the local interrupt mechanism for timer
> and software
> +interrupt to the Machine mode of hart. The operation parameters of
> local interrupt
> +is CLINT implementation-specific.
> +
> +===== Interrupt Assignments
>  
>  ==== System Peripherals
>  * UART/Serial Console
> @@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can
> meet the Embedded-2022
>  specification.
>  
>  ==== Interrupt Controller
> -Embedded systems are recommended to use a spec compliant
> -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> +Embedded systems are recommended to use a spec compliant
> <<PLICCLINT,PLIC>>, a spec compliant
>  
> https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
>  or both a CLIC and and PLIC.
>  


Sunil V L
 

Hi Abner,
On Wed, May 05, 2021 at 12:30:25PM +0800, renba.chang@... wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC + CLINT section of Linux-2022 platform.

In this commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
---
riscv-platform-spec.adoc | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..f9179fb 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,19 @@ include::profiles.adoc[]
* Start Address

==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to route
+the non-local global interrupts to the external interrupt of a hart context
Do we need both words - non-local and global ?

+with a given privilege mode in a given hart. The number of non-local interrupt
+sources supported by PLIC and how does each of them connect to the hart context
+is PLIC core implementation-specific. Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]
Should we just say implementation specific?

+for the PLIC operation parameters details. On the contrast, the Core Local
+Interrupt (CLINT) provides the local interrupt mechanism for timer and software
+interrupt to the Machine mode of hart. The operation parameters of local interrupt
+is CLINT implementation-specific.
The last sentence is not clear to me. Could you rephrase it?

I think you also need to add yourself to the contributors doc.

Regards
Sunil
+
+===== Interrupt Assignments

==== System Peripherals
* UART/Serial Console
@@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
specification.

==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant <<PLICCLINT,PLIC>>, a spec compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
or both a CLIC and and PLIC.

--
2.19.0.windows.1


Abner Chang
 

Sunil, do you know if CLINT would be deprecated? Will we have the equivalent functionality of CLINT in AIA?

Thanks
Abner

Sunil V L <sunilvl@...> 於 2021年5月5日 週三 下午4:23寫道:

Hi Abner,
On Wed, May 05, 2021 at 12:30:25PM +0800, renba.chang@... wrote:
> From: Abner Chang <renba.chang@...>
>
> Initial description of PLIC + CLINT section of Linux-2022 platform.
>
> In this commit,
> - Not sure where to put the [DEPRECATED].
> - Change the reference of PLIC in section 2.2.2. Interrupt Controller to
>   1.1.3.2 PLIC + CLINT section.
>
> Signed-off-by: Abner Chang <renba.chang@...>
> Cc: Alistair Francis <alistair.francis@...>
> Cc: Sunil V L <sunilvl@...>
> ---
>  riscv-platform-spec.adoc | 19 ++++++++++++++-----
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> index 160c74a..f9179fb 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -49,9 +49,19 @@ include::profiles.adoc[]
>  * Start Address

>  ==== Interrupt Controller
> -* AIA
> -* PLIC + CLINT
> -* Interrupt Assignments
> +===== AIA
> +===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]
> +The Platform Level Interrupt Controller (PLIC) provides facilities to route
> +the non-local global interrupts to the external interrupt of a hart context

Do we need both words -  non-local and global ?

> +with a given privilege mode in a given hart. The number of non-local interrupt
> +sources supported by PLIC and how does each of them connect to the hart context
> +is PLIC core implementation-specific. Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]

Should we just say implementation specific?

> +for the PLIC operation parameters details. On the contrast, the Core Local
> +Interrupt (CLINT) provides the local interrupt mechanism for timer and software
> +interrupt to the Machine mode of hart. The operation parameters of local interrupt
> +is CLINT implementation-specific.

The last sentence is not clear to me. Could you rephrase it?

I think you also need to add yourself to the contributors doc.

Regards
Sunil
> +
> +===== Interrupt Assignments

>  ==== System Peripherals
>  * UART/Serial Console
> @@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
>  specification.

>  ==== Interrupt Controller
> -Embedded systems are recommended to use a spec compliant
> -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> +Embedded systems are recommended to use a spec compliant <<PLICCLINT,PLIC>>, a spec compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
>  or both a CLIC and and PLIC.

> --
> 2.19.0.windows.1
>


Sunil V L
 

On Wed, May 05, 2021 at 05:51:26PM +0800, Abner Chang wrote:
Sunil, do you know if CLINT would be deprecated? Will we have the
equivalent functionality of CLINT in AIA?
As per my understanding,

1. AIA with both IMSIC and APLIC (Required)
2. PLIC + CLINT (deprecated)

I see supporting local interrupts as one of the major goal of the AIA
spec. So, I expect APLIC+IMSIC should support all use cases. IPI
chapter is TBD and hence we probably don't see some details.

There is some discussion regarding support for systems with APLIC only
(Without IMSIC). But that is still under discussion since in that case
APLIC needs to support IPI injection.

Thanks
Sunil

Thanks
Abner

Sunil V L <sunilvl@...> 於 2021年5月5日 週三 下午4:23寫道:

Hi Abner,
On Wed, May 05, 2021 at 12:30:25PM +0800, renba.chang@... wrote:
From: Abner Chang <renba.chang@...>

Initial description of PLIC + CLINT section of Linux-2022 platform.

In this commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
---
riscv-platform-spec.adoc | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..f9179fb 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,9 +49,19 @@ include::profiles.adoc[]
* Start Address

==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to
route
+the non-local global interrupts to the external interrupt of a hart
context

Do we need both words - non-local and global ?

+with a given privilege mode in a given hart. The number of non-local
interrupt
+sources supported by PLIC and how does each of them connect to the hart
context
+is PLIC core implementation-specific. Refer to
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
PLIC Specification]

Should we just say implementation specific?

+for the PLIC operation parameters details. On the contrast, the Core
Local
+Interrupt (CLINT) provides the local interrupt mechanism for timer and
software
+interrupt to the Machine mode of hart. The operation parameters of
local interrupt
+is CLINT implementation-specific.
The last sentence is not clear to me. Could you rephrase it?

I think you also need to add yourself to the contributors doc.

Regards
Sunil
+
+===== Interrupt Assignments

==== System Peripherals
* UART/Serial Console
@@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022
specification.

==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant
<<PLICCLINT,PLIC>>, a spec compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
or both a CLIC and and PLIC.

--
2.19.0.windows.1


Greg Favor
 

On Tue, May 4, 2021 at 9:48 PM Alistair Francis <alistair.francis@...> wrote:
From what I can tell in the AIA spec it doesn't include a replacement
for the CLINT. What should be used for mtime/mtimecmp instead?

AIA readily supports IPIs.  The placeholder IP chapter in AIA will describe the mechanics (which will be straightforward without needing to add any significant additional arch functionality to AIA).

As far as timer interrupts (both machine and supervisor level timer interrupts), the current architecture has dedicated bits in the interrupt-related CSRs for these, and AIA consciously avoids changing any of that.

More generally, AIA doesn't change local interrupt support; it just adds some standardization around this area of the arch spec since the spec currently doesn't say much.

Greg

 


Greg Favor
 

On Wed, May 5, 2021 at 3:12 AM Sunil V L <sunilvl@...> wrote:
1. AIA with both IMSIC and APLIC (Required)
2. PLIC + CLINT (deprecated)

I see supporting local interrupts as one of the major goal of the AIA
spec. So, I expect APLIC+IMSIC should support all use cases. IPI
chapter is TBD and hence we probably don't see some details.

AIA with IMSIC is sufficient to cover all the bases (except of course wired interrupts - which is what APLIC is for).  But if one only has an APLIC then the question of IPI support remains.  Either one requires IMSIC or APLIC is enhanced to support IPIs (which has been raised with John, the architect of AIA).  Based on recent discussions, the tentative stake in the ground is as stated above (but that certainly is not cast in concrete and remains an outstanding issue).
 
Greg


Jonathan Behrens <behrensj@...>
 

AIA doesn't have any support for timer interrupts. Which means that a CLINT is still going to be necessary unless / until there is some other way of doing timer interrupts.

Jonathan


On Wed, May 5, 2021 at 11:40 AM Greg Favor via lists.riscv.org <gfavor=ventanamicro.com@...> wrote:
On Wed, May 5, 2021 at 3:12 AM Sunil V L <sunilvl@...> wrote:
1. AIA with both IMSIC and APLIC (Required)
2. PLIC + CLINT (deprecated)

I see supporting local interrupts as one of the major goal of the AIA
spec. So, I expect APLIC+IMSIC should support all use cases. IPI
chapter is TBD and hence we probably don't see some details.

AIA with IMSIC is sufficient to cover all the bases (except of course wired interrupts - which is what APLIC is for).  But if one only has an APLIC then the question of IPI support remains.  Either one requires IMSIC or APLIC is enhanced to support IPIs (which has been raised with John, the architect of AIA).  Based on recent discussions, the tentative stake in the ground is as stated above (but that certainly is not cast in concrete and remains an outstanding issue).
 
Greg


Greg Favor
 

On Wed, May 5, 2021 at 9:06 AM Jonathan Behrens <behrensj@...> wrote:
AIA doesn't have any support for timer interrupts. Which means that a CLINT is still going to be necessary unless / until there is some other way of doing timer interrupts.

Thanks, and yes I misspoke.  While the new Sstc arch extension will provide Supervisor timer support, a subset of CLINT-like functionality - just the Machine timer support - still seems necessary to specify. ( Or am I missing something further?)

Put a little differently, for the AIA case the platform spec should specify the CLINT-like mtime/mtimecmp hardware (e.g. registers, register layout, etc.).

Btw, is there an "official" CLINT spec that all implementations currently match?  Or is there variability?

Greg


Anup Patel
 

There are variations in CLINT implementation across existing RISC-V systems. For example, the Andes Tech RISC-V SOCs have their own CLINT variant which does not align with SiFive CLINT.

 

Another problem is that CLINT spec is not part of the specs owned by RISC-V international. The only CLINT documentation available is part of SiFive SOC documentation.

 

The IPI support and Timer support are critical pieces for a Linux capable system so we need standardized approach for both of these.

 

Like Greg mentioned, the AIA spec can take care of the IPI support (under discussion) and “Sstc” extension takes care of S-mode timer support. The only missing piece is a standard M-mode timer support.

 

I suggest we have dedicated RISC-V M-mode timer chapter in the RISC-V platform spec (or a separate specification). This chapter will describe a M-mode timer device with memory mapped mtime and mtimecmp registers which complies with “3.1.10 Machine Timer Registers” of the RISC-V privilege specification. We can align the M-mode timer device with CLINT, where mtime register is at 0x4000 offset and per-HART mtimecmp registers start at 0xbff8 offset.

 

Regards,

Anup

 

From: tech-unixplatformspec@... <tech-unixplatformspec@...> On Behalf Of Greg Favor
Sent: 05 May 2021 22:36
To: Jonathan Behrens <behrensj@...>
Cc: Sunil V L <sunilvl@...>; Abner Chang <renba.chang@...>; tech-unixplatformspec@...; Chang, Abner <abner.chang@...>; Alistair Francis <Alistair.Francis@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

On Wed, May 5, 2021 at 9:06 AM Jonathan Behrens <behrensj@...> wrote:

AIA doesn't have any support for timer interrupts. Which means that a CLINT is still going to be necessary unless / until there is some other way of doing timer interrupts.

 

Thanks, and yes I misspoke.  While the new Sstc arch extension will provide Supervisor timer support, a subset of CLINT-like functionality - just the Machine timer support - still seems necessary to specify. ( Or am I missing something further?)

 

Put a little differently, for the AIA case the platform spec should specify the CLINT-like mtime/mtimecmp hardware (e.g. registers, register layout, etc.).

 

Btw, is there an "official" CLINT spec that all implementations currently match?  Or is there variability?

 

Greg

 


Abner Chang
 



Anup Patel <Anup.Patel@...> 於 2021年5月6日 週四 上午11:45寫道:

There are variations in CLINT implementation across existing RISC-V systems. For example, the Andes Tech RISC-V SOCs have their own CLINT variant which does not align with SiFive CLINT.

 

Another problem is that CLINT spec is not part of the specs owned by RISC-V international. The only CLINT documentation available is part of SiFive SOC documentation.

 

The IPI support and Timer support are critical pieces for a Linux capable system so we need standardized approach for both of these.

 

Like Greg mentioned, the AIA spec can take care of the IPI support (under discussion) and “Sstc” extension takes care of S-mode timer support. The only missing piece is a standard M-mode timer support.

 

I suggest we have dedicated RISC-V M-mode timer chapter in the RISC-V platform spec (or a separate specification). This chapter will describe a M-mode timer device with memory mapped mtime and mtimecmp registers which complies with “3.1.10 Machine Timer Registers” of the RISC-V privilege specification. We can align the M-mode timer device with CLINT, where mtime register is at 0x4000 offset and per-HART mtimecmp registers start at 0xbff8 offset.

 
So that would be CLINT is not deprecated but only support M-mode timer at the moment.  I will separate CLINT from the PLIC+CLINT section, DEPRECATED for PLIC. Add one new subsection for CLINT that says only support M-mode timer. 
CLINT base address is implementation-specific, but offset 0x4000 is per hart mtimecmp and 0xbff8 is mtime (it is swapped according to SiFive SoC spec)
Make sense?

Abner

 

Regards,

Anup

 

From: tech-unixplatformspec@... <tech-unixplatformspec@...> On Behalf Of Greg Favor
Sent: 05 May 2021 22:36
To: Jonathan Behrens <behrensj@...>
Cc: Sunil V L <sunilvl@...>; Abner Chang <renba.chang@...>; tech-unixplatformspec@...; Chang, Abner <abner.chang@...>; Alistair Francis <Alistair.Francis@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

On Wed, May 5, 2021 at 9:06 AM Jonathan Behrens <behrensj@...> wrote:

AIA doesn't have any support for timer interrupts. Which means that a CLINT is still going to be necessary unless / until there is some other way of doing timer interrupts.

 

Thanks, and yes I misspoke.  While the new Sstc arch extension will provide Supervisor timer support, a subset of CLINT-like functionality - just the Machine timer support - still seems necessary to specify. ( Or am I missing something further?)

 

Put a little differently, for the AIA case the platform spec should specify the CLINT-like mtime/mtimecmp hardware (e.g. registers, register layout, etc.).

 

Btw, is there an "official" CLINT spec that all implementations currently match?  Or is there variability?

 

Greg

 


Abner Chang
 



Sunil V L <sunilvl@...> 於 2021年5月5日 週三 下午4:23寫道:
Hi Abner,
On Wed, May 05, 2021 at 12:30:25PM +0800, renba.chang@... wrote:
> From: Abner Chang <renba.chang@...>
>
> Initial description of PLIC + CLINT section of Linux-2022 platform.
>
> In this commit,
> - Not sure where to put the [DEPRECATED].
> - Change the reference of PLIC in section 2.2.2. Interrupt Controller to
>   1.1.3.2 PLIC + CLINT section.
>
> Signed-off-by: Abner Chang <renba.chang@...>
> Cc: Alistair Francis <alistair.francis@...>
> Cc: Sunil V L <sunilvl@...>
> ---
>  riscv-platform-spec.adoc | 19 ++++++++++++++-----
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> index 160c74a..f9179fb 100644
> --- a/riscv-platform-spec.adoc
> +++ b/riscv-platform-spec.adoc
> @@ -49,9 +49,19 @@ include::profiles.adoc[]
>  * Start Address

>  ==== Interrupt Controller
> -* AIA
> -* PLIC + CLINT
> -* Interrupt Assignments
> +===== AIA
> +===== PLIC + CLINT [DEPRECATED][[PLICCLINT]]
> +The Platform Level Interrupt Controller (PLIC) provides facilities to route
> +the non-local global interrupts to the external interrupt of a hart context

Do we need both words -  non-local and global ?
no, I missed cleaning this up. Non-local is good enough.

> +with a given privilege mode in a given hart. The number of non-local interrupt
> +sources supported by PLIC and how does each of them connect to the hart context
> +is PLIC core implementation-specific. Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]

Should we just say implementation specific?
The  " implementation-specific" is for the number of non-local interrupt sources and the hart context each interrupt source connects to. The "implementation-specific" is not for the operation parameters such as memory map register and bit map for the register. Operation parameters of PLIC have to be standardized for the firmware implementation at least, although PLIC is going to be deprecated.

> +for the PLIC operation parameters details. On the contrast, the Core Local
> +Interrupt (CLINT) provides the local interrupt mechanism for timer and software
> +interrupt to the Machine mode of hart. The operation parameters of local interrupt
> +is CLINT implementation-specific.

The last sentence is not clear to me. Could you rephrase it?
Sure, I will rephrase it with the feedback from the discussion. 

I think you also need to add yourself to the contributors doc.
ok, thanks

Abner 

Regards
Sunil
> +
> +===== Interrupt Assignments

>  ==== System Peripherals
>  * UART/Serial Console
> @@ -289,8 +299,7 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
>  specification.

>  ==== Interrupt Controller
> -Embedded systems are recommended to use a spec compliant
> -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> +Embedded systems are recommended to use a spec compliant <<PLICCLINT,PLIC>>, a spec compliant
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
>  or both a CLIC and and PLIC.

> --
> 2.19.0.windows.1
>


Greg Favor
 

On Wed, May 5, 2021 at 8:45 PM Anup Patel <Anup.Patel@...> wrote:

I suggest we have dedicated RISC-V M-mode timer chapter in the RISC-V platform spec (or a separate specification). This chapter will describe a M-mode timer device with memory mapped mtime and mtimecmp registers which complies with “3.1.10 Machine Timer Registers” of the RISC-V privilege specification. We can align the M-mode timer device with CLINT, where mtime register is at 0x4000 offset and per-HART mtimecmp registers start at 0xbff8 offset.


I completely agree.  This can be a short and simple resolution to the problem.

Anup, could you send a copy of or pointer to a suitable version of a CLINT spec?

Greg
 


Greg Favor
 

On Wed, May 5, 2021 at 9:09 PM Abner Chang <renba.chang@...> wrote:
So that would be CLINT is not deprecated but only support M-mode timer at the moment.  I will separate CLINT from the PLIC+CLINT section, DEPRECATED for PLIC. Add one new subsection for CLINT that says only support M-mode timer. 
CLINT base address is implementation-specific, but offset 0x4000 is per hart mtimecmp and 0xbff8 is mtime (it is swapped according to SiFive SoC spec)
Make sense?

Since there is not an official RVI spec for CLINT, we should not be referring to it for functionality that is not going to be deprecated.  (It's bad enough that a standard platform spec is going to require (as one option) an unstandardized component.)  We should do as Anup suggested and have a separate standalone spec of the Machine timer support.

Greg


Abner Chang
 



Greg Favor <gfavor@...> 於 2021年5月6日 週四 下午3:27寫道:
On Wed, May 5, 2021 at 9:09 PM Abner Chang <renba.chang@...> wrote:
So that would be CLINT is not deprecated but only support M-mode timer at the moment.  I will separate CLINT from the PLIC+CLINT section, DEPRECATED for PLIC. Add one new subsection for CLINT that says only support M-mode timer. 
CLINT base address is implementation-specific, but offset 0x4000 is per hart mtimecmp and 0xbff8 is mtime (it is swapped according to SiFive SoC spec)
Make sense?

Since there is not an official RVI spec for CLINT, we should not be referring to it for functionality that is not going to be deprecated.  (It's bad enough that a standard platform spec is going to require (as one option) an unstandardized component.)  We should do as Anup suggested and have a separate standalone spec of the Machine timer support.

Hi Greg, so you prefer to have a separate spec for the Machine timer? Because Anup was suggested to have a dedicated RISC-V M-mode timer chapter in the RISC-V platform spec or a separate specification.
If so, I will just simply mention CLINT has to support Machine mode timer.

Abner

Greg


Greg Favor
 

On Thu, May 6, 2021, 12:41 AM Abner Chang <renba.chang@...> wrote:

Hi Greg, so you prefer to have a separate spec for the Machine timer? Because Anup was suggested to have a dedicated RISC-V M-mode timer chapter in the RISC-V platform spec or a separate specification.
If so, I will just simply mention CLINT has to support Machine mode timer.


A dedicated chapter as Anup suggested, but a standalone spec that is not dependent on or referring to a (non-standard) CLINT spec.

Greg


Abner Chang
 

Got you.

Greg Favor <gfavor@...> 於 2021年5月6日 週四 下午4:02寫道:

On Thu, May 6, 2021, 12:41 AM Abner Chang <renba.chang@...> wrote:

Hi Greg, so you prefer to have a separate spec for the Machine timer? Because Anup was suggested to have a dedicated RISC-V M-mode timer chapter in the RISC-V platform spec or a separate specification.
If so, I will just simply mention CLINT has to support Machine mode timer.


A dedicated chapter as Anup suggested, but a standalone spec that is not dependent on or referring to a (non-standard) CLINT spec.

Greg


Anup Patel
 

Yes, it will be better to have small independent spec for the RISC-V M-mode timer (or “RISC-V mtimer”) so that it can be cited from different places.

 

This spec can be hosted under github.com/riscv/riscv-mtimer. Suggestions ??

 

Who is willing to volunteer for the initial draft ??? Abner ???

 

Regards,

Anup

 

From: Abner Chang <renba.chang@...>
Sent: 06 May 2021 13:38
To: Greg Favor <gfavor@...>
Cc: Anup Patel <Anup.Patel@...>; Jonathan Behrens <behrensj@...>; Sunil V L <sunilvl@...>; tech-unixplatformspec@...; Alistair Francis <Alistair.Francis@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

Got you.

 

Greg Favor <gfavor@...> 202156 週四 下午4:02寫道:

On Thu, May 6, 2021, 12:41 AM Abner Chang <renba.chang@...> wrote:

 

Hi Greg, so you prefer to have a separate spec for the Machine timer? Because Anup was suggested to have a dedicated RISC-V M-mode timer chapter in the RISC-V platform spec or a separate specification.

If so, I will just simply mention CLINT has to support Machine mode timer.

 

 

A dedicated chapter as Anup suggested, but a standalone spec that is not dependent on or referring to a (non-standard) CLINT spec.

 

Greg


Anup Patel
 

Hi Greg,

 

Refer Chapter9 of https://static.dev.sifive.com/FU540-C000-v1.0.pdf

OR

Refer Chapter11 of https://sifive.cdn.prismic.io/sifive/28560457-c5a4-4f88-866c-8098d02afea1_FU740-C000-Manual-v1p0.pdf

 

Regards,

Anup

 

From: Greg Favor <gfavor@...>
Sent: 06 May 2021 12:51
To: Anup Patel <Anup.Patel@...>
Cc: Jonathan Behrens <behrensj@...>; Sunil V L <sunilvl@...>; Abner Chang <renba.chang@...>; tech-unixplatformspec@...; Chang, Abner <abner.chang@...>; Alistair Francis <Alistair.Francis@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH] riscv-platform-spec: PLIC and CLINT for Linux-2022 platform

 

On Wed, May 5, 2021 at 8:45 PM Anup Patel <Anup.Patel@...> wrote:

I suggest we have dedicated RISC-V M-mode timer chapter in the RISC-V platform spec (or a separate specification). This chapter will describe a M-mode timer device with memory mapped mtime and mtimecmp registers which complies with “3.1.10 Machine Timer Registers” of the RISC-V privilege specification. We can align the M-mode timer device with CLINT, where mtime register is at 0x4000 offset and per-HART mtimecmp registers start at 0xbff8 offset.

 

I completely agree.  This can be a short and simple resolution to the problem.

 

Anup, could you send a copy of or pointer to a suitable version of a CLINT spec?

 

Greg