Date 1 - 1 of 1
[PATCH v2] Add an ISA requirement section
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There are few ISA level requirements/strong recommendations that platform
should follow. Create an new subsection to contain all these requirements.
Move the user-level requirements from user.doc to here as well.
Signed-off-by: Atish Patra <atish.patra@...>
Makefile | 3 +--
riscv-platform-spec.adoc | 24 ++++++++++++++++++++----
user-level.adoc | 17 -----------------
3 files changed, 21 insertions(+), 23 deletions(-)
delete mode 100644 user-level.adoc
diff --git a/Makefile b/Makefile
index 9556ace700d5..48e8fe9883ed 100644
@@ -7,8 +7,7 @@ DITAA = ditaa
IMAGES = pcie-topology.png
PLATFORM_SPEC = riscv-platform-spec
PANDOC = pandoc
-PARTS = changelog.adoc contributors.adoc introduction.adoc licensing.adoc \
+PARTS = changelog.adoc contributors.adoc introduction.adoc licensing.adoc
# Build the platform spec in several formats
all: $(IMAGES) $(PLATFORM_SPEC).md $(PLATFORM_SPEC).pdf $(PLATFORM_SPEC).html
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 394304bd6778..e9b295b9802d 100644
@@ -108,15 +108,31 @@ The M platform has the following extensions:
// Base feature set for OS-A Platform
-* ISA Profile
+* ISA Requirements
** The OS-A platform is required to comply with the RVA22 profile.
-* Cache Coherency
+** Within main-memory regions, aligned instruction fetch must be atomic, up to
+ the smaller of ILEN and XLEN bits. In particular, if an aligned 4-byte word
+ is stored with the `sw` instruction, then any processor attempts to execute
+ that word, the processor either fetches the newly stored word, or some previous
+ value stored to that location. (That is, the fetched instruction is not an
+ unpredictable value, nor is it a hybrid of the bytes of the old and new
+** Platforms is allowed to operate only in little-endian mode i.e.
+ implementations must hardwire the mstatus.MBE field to 0.
+User-mode programs should not execute the `fence.i` instruction.
+* Cache Coherency
** All harts must adhere to the RVWMO memory model.
** All hart PMA regions for main memory must be marked as coherent.
-** Memory accesses by I/O masters can be coherent or non-coherent with respect
+** Memory accesses by I/O masters can be coherent or non-coherent with respect
to all hart-related caches.
The RVA22 profile defines 32 PMU counters out-of-which first three counters are
diff --git a/user-level.adoc b/user-level.adoc
deleted file mode 100644
@@ -1,17 +0,0 @@
-// SPDX-License-Indentifer: CC-BY-4.0
-// user-level.adoc: original User Level Platform content
-// This is material from the very first draft of the spec.
-## User-Level Platform
-* Within main-memory regions, aligned instruction fetch must be atomic, up to
- the smaller of ILEN and XLEN bits. In particular, if an aligned 4-byte word
- is stored with the `sw` instruction, then any processor attempts to execute
- that word, the processor either fetches the newly stored word, or some previous
- value stored to that location. (That is, the fetched instruction is not an
- unpredictable value, nor is it a hybrid of the bytes of the old and new
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