I notice many uses of the word "recommend".  My understanding is that there should be no recommendations in the platform spec - just requirements.  (To be more precise, I believe the Platforms Policy doc puts non-normative content in separate chapters.)

Greg

On Fri, May 7, 2021 at 9:01 AM Abner Chang <renba.chang@...> wrote:

From: Abner Chang <renba.chang@...>

Initial description of PLIC  CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

On v3 commit,
- Address review comments.

On v2 commit,
- CLINT is not deprecated.

- Add a standalone section for Machine Mode Timer in System Peripherals.
  Do you think this is a good place for Machine Mode Timer?
  @Mayuresh, please check if you are ok with this change, not sure if this
  overlaps with your text or not (The timer setion). I can remove this
  if you prefer to put this with your patch.

- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
  section and CLINT in Linux-2022 Platform.
  @Alistair, is this ok?

On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller to
  1.1.3.2 PLIC + CLINT section.

Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
---
 riscv-platform-spec.adoc | 88 +++++++++++++++++++++++-----------------
 1 file changed, 50 insertions(+), 38 deletions(-)

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..91c2abb 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -49,14 +49,56 @@ include::profiles.adoc[]
 * Start Address

 ==== Interrupt Controller
-* AIA
-* PLIC + CLINT
-* Interrupt Assignments
+===== AIA
+===== PLIC[DEPRECATED][[PLIC]]
+The Platform Level Interrupt Controller (PLIC) provides facilities to route
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local interrupt
+sources supported by PLIC and how does each of them connect to the hart
+context is PLIC core implementation-specific. +
+(Refer to https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V PLIC Specification]
+for the implementation reference of PLIC operation parameters)
+
+===== CLINT[[CLINT]]
+On the contrast to PLIC, the Core Local Interrupt (CLINT) provides
+facilities to trigger local interrupt of <<MachineModeTimer,Machine mode timer>>
+to hart.
+
+===== Interrupt Assignments

 ==== System Peripherals
 * UART/Serial Console
 * Clocks
 * Timers
+
+===== Machine Mode Timer[[MachineModeTimer]]
+Machine mode timer is required for Linux-2022 platform and incorporate with
+CLINT for the local interrupt to hart. The format of the operation parameters
+(`mtime` and `mtimecmp` registers) must compliant with RISC-V Privilege
+specification section 3.1.10. The base address of the memory map registers
+of Machine mode timer is platform implementation-specific, however the offset
+of `mtime` and `mtimecmp` registers are fixed as below,
+
+.Registers layout of mtimecmp
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
+|`0x4000` |mtimecmp for hart 0 |mtimecmp low for hart 0
+|`0x4004` ||mtimecmp high for hart 0
+|`0x4008` |mtimecmp for hart 1 |mtimecmp low for hart 1
+|`0x400c` ||mtimecmp high for hart 1
+|... ||
+|`0xbff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
+|`0xbff4` ||mtimecmp high for hart 4094
+|=======
+
+.Registers layout of mtime
+[width="60%",cols="1,^3,^3"]
+|=======
+|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for RV32*
+|`0xbff8` |mtime|mtime low
+|`0xbffc` ||mtime high
+|=======
 * Watchdog Timers

 ==== Boot Process
@@ -289,9 +331,8 @@ Any RISC-V system that uses at least RV32/64G can meet the Embedded-2022
 specification.

 ==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
-https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
+Embedded systems are recommended to use a spec compliant <<PLIC,PLIC>>, a spec
+compliant https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
 or both a CLIC and and PLIC.

 If using just a PLIC the system must continue to use the original basic
@@ -303,38 +344,9 @@ must be supported.
 Embedded systems cannot use a non-compliant interrupt controller and still
 call it a PLIC or CLIC.

-==== Machine Timer
-The RISC-V machine timer (controlled via `mtime` and `mtimecmp`) must be
-implemented. The two registers must be memory mapped as required by the RISC-V
-specification.
-
-The Embedded-2022 specification requires that the registers be mapped
-adjacent to each other with the `mtime` region at the lower address.
-
-The starting address of this region can be located anywhere in
-memory, including inside other peripherals, as long as the start address is
-4 byte aligned.
-
-An example of the memory layout for a 32-bit system with a single hart is below
-
--------------------------
-=========================
-| 0x00 |  mtime low     |
-| 0x04 |  mtime high    |
-| 0x08 |  mtimecmp low  |
-| 0x0C |  mtimecmp high |
-=========================
--------------------------
-
-and for a 64-bit system with 2 harts
-
----------------------------
-===========================
-| 0x00 |  mtime           |
-| 0x08 |  mtimecmp hart 1 |
-| 0x10 |  mtimecmp hart 2 |
-===========================
----------------------------
+==== Machine Mode Timer
+The Embedded-2022 specification requires RISC-V <<MachineModeTimer,Machine mode timer>>
+to be implemented and incorporated with the Core Local Interrupt (<<CLINT, CLINT>>).

 ==== Memory Map
 It is recommended that main memory and loadable code (not ROM) start at
--
2.19.0.windows.1

Hi Greg,

There is no "recommend" in this patch, I think we can create an issue for this on Github.

Initial description of PLIC  CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

On Fri, May 7, 2021 at 9:43 AM Abner Chang <renba.chang@...> wrote:

Hi Greg,

There is no "recommend" in this patch, I think we can create an issue for this on Github.

I think (?) we are meaning the same thing:  There is new text that uses the word "recommend", and all such uses need to be removed and turned into more appropropriate text (e.g. requirements).  Which is what the GH issue will cover.  Here's one example of what I'm referring to:

+Embedded systems are recommended to use a spec compliant <<PLIC,PLIC>>, a spec

Greg

On Fri, May 7, 2021 at 9:01 AM Abner Chang <renba.chang@...> wrote:

Initial description of PLIC  CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

I think we need a two-part treatment of the M-mode timer requirements.

For the "legacy/deprecated" PLIC+CLINT requirement, the platform spec should contain separate chapters that provide specs of the required PLIC and CLINT.  When this requirement gets removed in the 2024 platform spec, these chapters will simply disappear.

For the "new" AIA+"M-mode timer" requirement, the platform spec should contain a separate chapter that specs just the M-mode timer hardware.  This happens to be a subset of the above CLINT spec, but should be a standalone spec (especially since the CLINT chapter will eventually go away).

In the "M-mode timer" chapter, the offsets should be rebased to 0x0, i.e. the mtimecmp registers start at offset 0x0000, and mtime is at 0x7FF8.

Greg

 

In the "M-mode timer" chapter, the offsets should be rebased to 0x0, i.e. the mtimecmp registers start at offset 0x0000, and mtime is at 0x7FF8.

The Offset 0 is Software interrupt registers. Rebase those mtime registers to 0x0 is not compliant with SiFive spec and the opensbi CLINT implementation.

On Fri, May 7, 2021 at 7:15 PM Abner Chang <renba.chang@...> wrote:

In the "M-mode timer" chapter, the offsets should be rebased to 0x0, i.e. the mtimecmp registers start at offset 0x0000, and mtime is at 0x7FF8.

The Offset 0 is Software interrupt registers. Rebase those mtime registers to 0x0 is not compliant with SiFive spec and the opensbi CLINT implementation.

What I meant would be fully compatible with the SiFive spec.  The point is that when the "M-mode timer" spec has nothing in the first 16KiB of what is the CLINT memory map, one would specify the base address of the "M-mode timer" block of registers as the address of the first "M-mode timer" register.  One would not specify a base address for the "M-mode timer" registers to start four pages before the beginning of the block of "M-mode timer" registers.  No one normally ever would do that.

Put differently, when a CLINT is present, the base address would be for the beginning of the block of CLINT registers.  And when just  "M-mode timer" registers are present, the base address would be for the beginning of the block of "M-mode timer" registers.

Greg

Greg Favor <gfavor@...> 於 2021年5月8日 週六 上午11:53寫道：

What I meant would be fully compatible with the SiFive spec.  The point is that when the "M-mode timer" spec has nothing in the first 16KiB of what is the CLINT memory map, one would specify the base address of the "M-mode timer" block of registers as the address of the first "M-mode timer" register.  One would not specify a base address for the "M-mode timer" registers to start four pages before the beginning of the block of "M-mode timer" registers.  No one normally ever would do that.

Put differently, when a CLINT is present, the base address would be for the beginning of the block of CLINT registers.  And when just  "M-mode timer" registers are present, the base address would be for the beginning of the block of "M-mode timer" registers.

When the CLINT exists, the base address points to a block in which the software interrupt registers is the first block(0x00), My concern is we may have to introduce CLINT_MTIME_OFFSET (e.g. 0x4000) to the current opensbi CLINT implementation as the base address of mtime registers, thus mtime register block could be based at 0x0.  Are we on the same page or I miss something?  

BTW,  mtime should be at 0x3ff8 if mtimecmp is at offset 0x0.

On Sat, May 8, 2021 at 1:09 AM Abner Chang <renba.chang@...> wrote:

Greg Favor <gfavor@...> 於 2021年5月8日 週六 上午11:53寫道：

What I meant would be fully compatible with the SiFive spec.  The point is that when the "M-mode timer" spec has nothing in the first 16KiB of what is the CLINT memory map, one would specify the base address of the "M-mode timer" block of registers as the address of the first "M-mode timer" register.  One would not specify a base address for the "M-mode timer" registers to start four pages before the beginning of the block of "M-mode timer" registers.  No one normally ever would do that.

Put differently, when a CLINT is present, the base address would be for the beginning of the block of CLINT registers.  And when just  "M-mode timer" registers are present, the base address would be for the beginning of the block of "M-mode timer" registers.

When the CLINT exists, the base address points to a block in which the software interrupt registers is the first block(0x00), My concern is we may have to introduce CLINT_MTIME_OFFSET (e.g. 0x4000) to the current opensbi CLINT implementation as the base address of mtime registers, thus mtime register block could be based at 0x0.  Are we on the same page or I miss something?  

Cc'ing Anup and Atish who should be the ones to rule on how OpenSBI handles this issue.

The reasoning behind my suggestion below is that when CLINT disappears in the 2024 platform spec, there should not be permanent vestiges left lying around.  Someone three years from now shouldn't be wondering why the base address of the M-mode timer registers must be computed as something like (CLINT_BASE +  CLINT_MTIME_OFFSET) instead of, say, "MTIME_BASE" (especially when CLINT has no definition in that platform spec).

Since the two parts of CLINT are functionality separate and independent of each other, I suggest they have separate base addresses, e.g. "MSIP_BASE" and "MTIME_BASE".  When a CLINT is present, the latter will happen to be +0x4000 of the former.  In an AIA system the former goes away and one is cleanly left with just the latter.

 

BTW,  mtime should be at 0x3ff8 if mtimecmp is at offset 0x0.

I think my math was correct.  In a CLINT, mtime is at offset 0xBFF8.  Subtracting the offset 0x4000 (to the first mtimecmp register) results in 0x7FF8.

Greg

On Fri, 2021-05-07 at 09:25 -0700, Greg Favor wrote:
> I notice many uses of the word "recommend".  My understanding is that
> there should be no recommendations in the platform spec - just
> requirements.  (To be more precise, I believe the Platforms Policy
> doc puts non-normative content in separate chapters.)

Why are we removing recommendations?

For the embedded spec we don't want to force vendors to meet certain
requirements if they have a good reason not to. For example if they
share IP or memory maps across different product lines we want to allow
that. As that will make it easier for them and their customers to
transition to RISC-V.

On the other hand if vendors are picking addresses or IP we want to
encourage them to use a standard. Hence the recommendations.

Alistair

>
> Greg
>
>
> On Fri, May 7, 2021 at 9:01 AM Abner Chang <renba.chang@...>
> wrote:
> > From: Abner Chang <renba.chang@...>
> >
> > Initial description of PLIC  CLINT section of Linux-2022 platform.
> >
> > Is this what we want to see of CLINT/Machine mode timer in the
> > platform spec?
> >
> > On v3 commit,
> > - Address review comments.
> >
> > On v2 commit,
> > - CLINT is not deprecated.
> >
> > - Add a standalone section for Machine Mode Timer in System
> > Peripherals.
> >   Do you think this is a good place for Machine Mode Timer?
> >   @Mayuresh, please check if you are ok with this change, not sure
> > if
> > this
> >   overlaps with your text or not (The timer setion). I can remove
> > this
> >   if you prefer to put this with your patch.
> >
> > - In Embedded-2022, refer to Machine Mode Timer in System
> > Peripherals
> >   section and CLINT in Linux-2022 Platform.
> >   @Alistair, is this ok?
> >
> > On v1 commit,
> > - Not sure where to put the [DEPRECATED].
> > - Change the reference of PLIC in section 2.2.2. Interrupt
> > Controller
> > to
> >   1.1.3.2 PLIC + CLINT section.
> >
> > Signed-off-by: Abner Chang <renba.chang@...>
> > Cc: Alistair Francis <alistair.francis@...>
> > Cc: Sunil V L <sunilvl@...>
> > Cc: Mayuresh Chitale <mchitale@...>
> > ---
> >  riscv-platform-spec.adoc | 88 +++++++++++++++++++++++-------------
> > --
> > --
> >  1 file changed, 50 insertions(+), 38 deletions(-)
> >
> > diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
> > index 160c74a..91c2abb 100644
> > --- a/riscv-platform-spec.adoc
> > +++ b/riscv-platform-spec.adoc
> > @@ -49,14 +49,56 @@ include::profiles.adoc[]
> >  * Start Address
> >
> >  ==== Interrupt Controller
> > -* AIA
> > -* PLIC + CLINT
> > -* Interrupt Assignments
> > +===== AIA
> > +===== PLIC[DEPRECATED][[PLIC]]
> > +The Platform Level Interrupt Controller (PLIC) provides facilities
> > to route
> > +the non-local interrupts to the external interrupt of a hart
> > context
> > +with a given privilege mode in a given hart. The number of non-
> > local
> > interrupt
> > +sources supported by PLIC and how does each of them connect to the
> > hart
> > +context is PLIC core implementation-specific. +
> > +(Refer to
> > https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc[RISC-V
> > PLIC Specification]
> > +for the implementation reference of PLIC operation parameters)
> > +
> > +===== CLINT[[CLINT]]
> > +On the contrast to PLIC, the Core Local Interrupt (CLINT) provides
> > +facilities to trigger local interrupt of
> > <<MachineModeTimer,Machine
> > mode timer>>
> > +to hart.
> > +
> > +===== Interrupt Assignments
> >
> >  ==== System Peripherals
> >  * UART/Serial Console
> >  * Clocks
> >  * Timers
> > +
> > +===== Machine Mode Timer[[MachineModeTimer]]
> > +Machine mode timer is required for Linux-2022 platform and
> > incorporate with
> > +CLINT for the local interrupt to hart. The format of the operation
> > parameters
> > +(`mtime` and `mtimecmp` registers) must compliant with RISC-V
> > Privilege
> > +specification section 3.1.10. The base address of the memory map
> > registers
> > +of Machine mode timer is platform implementation-specific, however
> > the offset
> > +of `mtime` and `mtimecmp` registers are fixed as below,
> > +
> > +.Registers layout of mtimecmp
> > +[width="60%",cols="1,^3,^3"]
> > +|=======
> > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > +|`0x4000` |mtimecmp for hart 0 |mtimecmp low for hart 0
> > +|`0x4004` ||mtimecmp high for hart 0
> > +|`0x4008` |mtimecmp for hart 1 |mtimecmp low for hart 1
> > +|`0x400c` ||mtimecmp high for hart 1
> > +|... ||
> > +|`0xbff0` |mtimecmp for hart 4094|mtimecmp low for hart 4094
> > +|`0xbff4` ||mtimecmp high for hart 4094
> > +|=======
> > +
> > +.Registers layout of mtime
> > +[width="60%",cols="1,^3,^3"]
> > +|=======
> > +|*Offset*|*Register (8-byte) for RV64*|*Register (4-byte) for
> > RV32*
> > +|`0xbff8` |mtime|mtime low
> > +|`0xbffc` ||mtime high
> > +|=======
> >  * Watchdog Timers
> >
> >  ==== Boot Process
> > @@ -289,9 +331,8 @@ Any RISC-V system that uses at least RV32/64G
> > can
> > meet the Embedded-2022
> >  specification.
> >
> >  ==== Interrupt Controller
> > -Embedded systems are recommended to use a spec compliant
> > -https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
> > -
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> > +Embedded systems are recommended to use a spec compliant
> > <<PLIC,PLIC>>, a spec
> > +compliant
> > https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc[CLIC]
> >  or both a CLIC and and PLIC.
> >
> >  If using just a PLIC the system must continue to use the original
> > basic
> > @@ -303,38 +344,9 @@ must be supported.
> >  Embedded systems cannot use a non-compliant interrupt controller
> > and
> > still
> >  call it a PLIC or CLIC.
> >
> > -==== Machine Timer
> > -The RISC-V machine timer (controlled via `mtime` and `mtimecmp`)
> > must be
> > -implemented. The two registers must be memory mapped as required
> > by
> > the RISC-V
> > -specification.
> > -
> > -The Embedded-2022 specification requires that the registers be
> > mapped
> > -adjacent to each other with the `mtime` region at the lower
> > address.
> > -
> > -The starting address of this region can be located anywhere in
> > -memory, including inside other peripherals, as long as the start
> > address is
> > -4 byte aligned.
> > -
> > -An example of the memory layout for a 32-bit system with a single
> > hart is below
> > -
> > --------------------------
> > -=========================
> > -| 0x00 |  mtime low     |
> > -| 0x04 |  mtime high    |
> > -| 0x08 |  mtimecmp low  |
> > -| 0x0C |  mtimecmp high |
> > -=========================
> > --------------------------
> > -
> > -and for a 64-bit system with 2 harts
> > -
> > ----------------------------
> > -===========================
> > -| 0x00 |  mtime           |
> > -| 0x08 |  mtimecmp hart 1 |
> > -| 0x10 |  mtimecmp hart 2 |
> > -===========================
> > ----------------------------
> > +==== Machine Mode Timer
> > +The Embedded-2022 specification requires RISC-V
> > <<MachineModeTimer,Machine mode timer>>
> > +to be implemented and incorporated with the Core Local Interrupt
> > (<<CLINT, CLINT>>).
> >
> >  ==== Memory Map
> >  It is recommended that main memory and loadable code (not ROM)
> > start
> > at

On Fri, May 7, 2021 at 9:01 AM Abner Chang <renba.chang@...> wrote:

Initial description of PLIC  CLINT section of Linux-2022 platform.

Is this what we want to see of CLINT/Machine mode timer in the
platform spec?

I think we need a two-part treatment of the M-mode timer requirements.

For the "legacy/deprecated" PLIC+CLINT requirement, the platform spec should contain separate chapters that provide specs of the required PLIC and CLINT.  When this requirement gets removed in the 2024 platform spec, these chapters will simply disappear.

For the "new" AIA+"M-mode timer" requirement, the platform spec should contain a separate chapter that specs just the M-mode timer hardware.  This happens to be a subset of the above CLINT spec, but should be a standalone spec (especially since the CLINT chapter will eventually go away).

In the "M-mode timer" chapter, the offsets should be rebased to 0x0, i.e. the mtimecmp registers start at offset 0x0000, and mtime is at 0x7FF8.

Greg

 

Hi Greg,

I am going to restructure the sections for PLIC/CLINT/MTIMER. I am not quite sure your preference of  "separate chapters that provide specs of the required PLIC and CLINT". The chapters in riscv-platform-spec are based on the platform definition, thus I think to have separate sections is good enough. The structure of sections would be looked as below,

1.1.3. Interrupt Controller
1.1.3.1  AIA
1.1.3.2  PLIC + CLINT [DEPRECATED]
1.1.3.3. Interrupt Assignments

1.1.4. System Peripherals
1.1.4.1 UART/Serial Console
1.1.4.2. Clocks
1.1.4.3. Timers
1.1.4.4. ,Watchdog Timers

1.1.4.5. Machine Mode Timer

 

With the above, we can remove 1.1.3.2 section for Linux2024. Is this ok?

Regards,

Abner

In the "M-mode timer" chapter, the offsets should be rebased to 0x0, i.e. the mtimecmp registers start at offset 0x0000, and mtime is at 0x7FF8.

Greg