[PATCH v5 1/8] Additional requirements for H-extension
OS/A-server platforms must comply with additional requirements
for H-extension.
Also, the little-endian requirement in OS/A-base should be
more relaxed requiring implementation to set 0 in mstatus.MBE.
Signed-off-by: Anup Patel <anup.patel@...>
Reviewed-by: Alistair Francis <alistair.francis@...>
Reviewed-by: Atish Patra <atish.patra@...>
---
riscv-platform-spec.adoc | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 95f0c7b..44a7012 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -123,8 +123,26 @@ The M platform has the following extensions:
value stored to that location. (That is, the fetched instruction is not an
unpredictable value, nor is it a hybrid of the bytes of the old and new
values.)
-** Platforms is allowed to operate only in little-endian mode i.e.
- implementations must hardwire the mstatus.MBE field to 0.
+** When an illegal instruction trap is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtval` CSR.
+** When an illegal instruction trap is taken into S-mode, exception-specific
+ non-zere value must be written to the `stval` CSR.
+** Platform must operate in little-endian mode (i.e. implementations must
+ set the mstatus.MBE field to 0).
+** If the RISC-V ISA H-extension is implemented then the OS-A platform must
+ comply with the following additional requirements:
+*** When virtual instruction trap is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtval` CSR.
+*** When virtual instruction trap is taken into S-mode, exception-specific
+ non-zero must be written to the `stval` CSR.
+*** When guest page fault is taken into M-mode, exception-specific
+ information must be written to the `mtval2` CSR.
+*** When guest page fault is taken into S-mode, exception-specific
+ information value must be written to the `htval` CSR.
+*** When load/store/AMO fault is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtinst` CSR.
+*** When load/store/AMO fault is taken into S-mode, exception-specific
+ non-zero value must be written to the `htinst` CSR.
[sidebar]
--
@@ -462,9 +480,9 @@ base with the additional requirements as below.
==== Architecture
The platforms which conform to server extension are required to implement +
-- RV64 support
-- RISC-V H ISA extension
-- VMID support
+* RV64 support
+* RISC-V ISA H-extension with following additional requirements:
+** VMID support
==== PMU
--
2.25.1
To have a meaningful H-extension support, both OS/A-base and
OS/A-server platforms must comply with additional requirements
for H-extension.
Also, the little-endian requirement in OS/A-base should be
more relaxed requiring implementation to set 0 in mstatus.MBE.
Signed-off-by: Anup Patel <anup.patel@...>
Reviewed-by: Alistair Francis <alistair.francis@...>
Reviewed-by: Atish Patra <atish.patra@...>
---
riscv-platform-spec.adoc | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 95f0c7b..44a7012 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -123,8 +123,26 @@ The M platform has the following extensions:
value stored to that location. (That is, the fetched instruction is not an
unpredictable value, nor is it a hybrid of the bytes of the old and new
values.)
-** Platforms is allowed to operate only in little-endian mode i.e.
- implementations must hardwire the mstatus.MBE field to 0.
+** When an illegal instruction trap is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtval` CSR.
+** When an illegal instruction trap is taken into S-mode, exception-specific
+ non-zere value must be written to the `stval` CSR.
+** Platform must operate in little-endian mode (i.e. implementations must
+ set the mstatus.MBE field to 0).
+** If the RISC-V ISA H-extension is implemented then the OS-A platform must
+ comply with the following additional requirements:
+*** When virtual instruction trap is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtval` CSR.
+*** When virtual instruction trap is taken into S-mode, exception-specific
+ non-zero must be written to the `stval` CSR.
+*** When guest page fault is taken into M-mode, exception-specific
+ information must be written to the `mtval2` CSR.
+*** When guest page fault is taken into S-mode, exception-specific
+ information value must be written to the `htval` CSR.
+*** When load/store/AMO fault is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtinst` CSR.
+*** When load/store/AMO fault is taken into S-mode, exception-specific
+ non-zero value must be written to the `htinst` CSR.
[sidebar]
--
@@ -462,9 +480,9 @@ base with the additional requirements as below.
==== Architecture
The platforms which conform to server extension are required to implement +
-- RV64 support
-- RISC-V H ISA extension
-- VMID support
+* RV64 support
+* RISC-V ISA H-extension with following additional requirements:
+** VMID support
==== PMU
--
2.25.1
You are right, we can’t say exception specific non-zero value here.
Also, same is true for virtual instruction trap as well.
Let me quickly re-phrase this.
Regards,
Anup
From: <tech-unixplatformspec@...> on behalf of Jonathan Behrens <behrensj@...>
Date: Wednesday, 11 August 2021 at 6:34 PM
To: Anup Patel <Anup.Patel@...>
Cc: "tech-unixplatformspec@..." <tech-unixplatformspec@...>, Kumar Sankaran <ksankaran@...>, Atish Patra <Atish.Patra@...>, Alistair Francis <Alistair.Francis@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [PATCH v5 1/8] Additional requirements for H-extension
+** When an illegal instruction trap is taken into S-mode, exception-specific
+ non-zere value must be written to the `stval` CSR.
nit: When the illegal instruction is c.unimp (encoded as 0x0000) then the exception specific value is zero, and there is no compliant way to write a non-zero value.
To have a meaningful H-extension support, both OS/A-base and
OS/A-server platforms must comply with additional requirements
for H-extension.
Also, the little-endian requirement in OS/A-base should be
more relaxed requiring implementation to set 0 in mstatus.MBE.
Signed-off-by: Anup Patel <anup.patel@...>
Reviewed-by: Alistair Francis <alistair.francis@...>
Reviewed-by: Atish Patra <atish.patra@...>
---
riscv-platform-spec.adoc | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 95f0c7b..44a7012 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -123,8 +123,26 @@ The M platform has the following extensions:
value stored to that location. (That is, the fetched instruction is not an
unpredictable value, nor is it a hybrid of the bytes of the old and new
values.)
-** Platforms is allowed to operate only in little-endian mode i.e.
- implementations must hardwire the mstatus.MBE field to 0.
+** When an illegal instruction trap is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtval` CSR.
+** When an illegal instruction trap is taken into S-mode, exception-specific
+ non-zere value must be written to the `stval` CSR.
+** Platform must operate in little-endian mode (i.e. implementations must
+ set the mstatus.MBE field to 0).
+** If the RISC-V ISA H-extension is implemented then the OS-A platform must
+ comply with the following additional requirements:
+*** When virtual instruction trap is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtval` CSR.
+*** When virtual instruction trap is taken into S-mode, exception-specific
+ non-zero must be written to the `stval` CSR.
+*** When guest page fault is taken into M-mode, exception-specific
+ information must be written to the `mtval2` CSR.
+*** When guest page fault is taken into S-mode, exception-specific
+ information value must be written to the `htval` CSR.
+*** When load/store/AMO fault is taken into M-mode, exception-specific
+ non-zero value must be written to the `mtinst` CSR.
+*** When load/store/AMO fault is taken into S-mode, exception-specific
+ non-zero value must be written to the `htinst` CSR.
[sidebar]
--
@@ -462,9 +480,9 @@ base with the additional requirements as below.
==== Architecture
The platforms which conform to server extension are required to implement +
-- RV64 support
-- RISC-V H ISA extension
-- VMID support
+* RV64 support
+* RISC-V ISA H-extension with following additional requirements:
+** VMID support
==== PMU
--
2.25.1