[tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Hi All,
The RISC-V ACLINT specification is now hosted on RISC-V GitHub page:
https://github.com/riscv/riscv-aclint
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc
Please review this at your end send feedback on AIA/Platform mailing
lists.
The RISC-V ACLINT specification is intended to be small and backward
compatible to the SiFive CLINT specification which makes existing
RISC-V platforms compliant with the RISC-V ACLINT specification.
Overall, from platforms specification perspective it complements
the RISC-V AIA specification by providing IPI and Timer functionality.
A complete functional implementation is available for QEMU RISC-V
along with OpenSBI and Linux RISC-V changes. Please refer, the
riscv_aclint_v1 branch in following repos:
https://github.com/avpatel/qemu.git
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
To enable ACLINT emulation on QEMU, use "-M virt,aclint=on"
instead of just "-M virt" in your QEMU command line. For now,
QEMU supports ACLINT only for virt machine.
Regards,
Anup
Hi Josh,
Indeed, I missed adding text regarding verifying delta and ensuring that it is within bounds. Thanks for pointing.
I was thinking that aclint_mtime_sync() function should return the adjustment value (delta) so that high-level caller can try acling_mtime_sync() few times until the returned adjustment (delta) becomes zero (or close to it).
Regards,
Anup
Sent: 27 May 2021 01:58
To: Anup Patel <Anup.Patel@...>
Cc: tech-aia@...; tech-unixplatformspec@...; Atish Patra <Atish.Patra@...>; Greg Favor <gfavor@...>; Alistair Francis <Alistair.Francis@...>; Andrew Waterman <andrew@...>; John Hauser <jh.riscv@...>
Subject: Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Thanks for writing this up, Anup.
In https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc#24-synchronizing-multiple-mtimer-devices, the SW algorithm should include verifying the reference-target delta, retrying if the delta is out of bounds, and / or reporting failure to verify the synchronization is in bounds.
-Josh
On Tue, May 25, 2021 at 10:18 PM Anup Patel <anup.patel@...> wrote:
Hi All,
The RISC-V ACLINT specification is now hosted on RISC-V GitHub page:
https://github.com/riscv/riscv-aclint
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc
Please review this at your end send feedback on AIA/Platform mailing
lists.
The RISC-V ACLINT specification is intended to be small and backward
compatible to the SiFive CLINT specification which makes existing
RISC-V platforms compliant with the RISC-V ACLINT specification.
Overall, from platforms specification perspective it complements
the RISC-V AIA specification by providing IPI and Timer functionality.
A complete functional implementation is available for QEMU RISC-V
along with OpenSBI and Linux RISC-V changes. Please refer, the
riscv_aclint_v1 branch in following repos:
https://github.com/avpatel/qemu.git
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
To enable ACLINT emulation on QEMU, use "-M virt,aclint=on"
instead of just "-M virt" in your QEMU command line. For now,
QEMU supports ACLINT only for virt machine.
Regards,
Anup
Hi Josh,
I have created a GitHub PR addressing your comments. Please check if you are okay with this.
https://github.com/riscv/riscv-aclint/pull/2
Regards,
Anup
Sent: 27 May 2021 01:58
To: Anup Patel <Anup.Patel@...>
Cc: tech-aia@...; tech-unixplatformspec@...; Atish Patra <Atish.Patra@...>; Greg Favor <gfavor@...>; Alistair Francis <Alistair.Francis@...>; Andrew Waterman <andrew@...>; John Hauser <jh.riscv@...>
Subject: Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Thanks for writing this up, Anup.
In https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc#24-synchronizing-multiple-mtimer-devices, the SW algorithm should include verifying the reference-target delta, retrying if the delta is out of bounds, and / or reporting failure to verify the synchronization is in bounds.
-Josh
On Tue, May 25, 2021 at 10:18 PM Anup Patel <anup.patel@...> wrote:
Hi All,
The RISC-V ACLINT specification is now hosted on RISC-V GitHub page:
https://github.com/riscv/riscv-aclint
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc
Please review this at your end send feedback on AIA/Platform mailing
lists.
The RISC-V ACLINT specification is intended to be small and backward
compatible to the SiFive CLINT specification which makes existing
RISC-V platforms compliant with the RISC-V ACLINT specification.
Overall, from platforms specification perspective it complements
the RISC-V AIA specification by providing IPI and Timer functionality.
A complete functional implementation is available for QEMU RISC-V
along with OpenSBI and Linux RISC-V changes. Please refer, the
riscv_aclint_v1 branch in following repos:
https://github.com/avpatel/qemu.git
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
To enable ACLINT emulation on QEMU, use "-M virt,aclint=on"
instead of just "-M virt" in your QEMU command line. For now,
QEMU supports ACLINT only for virt machine.
Regards,
Anup
Hi Josh,
I have created a GitHub PR addressing your comments. Please check if you are okay with this.
https://github.com/riscv/riscv-aclint/pull/2
Regards,
Anup
From: tech-aia@... <tech-aia@...> On Behalf Of Josh Scheid
Sent: 27 May 2021 01:58
To: Anup Patel <Anup.Patel@...>
Cc: tech-aia@...; tech-unixplatformspec@...; Atish Patra <Atish.Patra@...>; Greg Favor <gfavor@...>; Alistair Francis <Alistair.Francis@...>; Andrew Waterman <andrew@...>; John Hauser <jh.riscv@...>
Subject: Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Thanks for writing this up, Anup.
In https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc#24-synchronizing-multiple-mtimer-devices, the SW algorithm should include verifying the reference-target delta, retrying if the delta is out of bounds, and / or reporting failure to verify the synchronization is in bounds.
-Josh
On Tue, May 25, 2021 at 10:18 PM Anup Patel <anup.patel@...> wrote:
Hi All,
The RISC-V ACLINT specification is now hosted on RISC-V GitHub page:
https://github.com/riscv/riscv-aclint
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc
Please review this at your end send feedback on AIA/Platform mailing
lists.
The RISC-V ACLINT specification is intended to be small and backward
compatible to the SiFive CLINT specification which makes existing
RISC-V platforms compliant with the RISC-V ACLINT specification.
Overall, from platforms specification perspective it complements
the RISC-V AIA specification by providing IPI and Timer functionality.
A complete functional implementation is available for QEMU RISC-V
along with OpenSBI and Linux RISC-V changes. Please refer, the
riscv_aclint_v1 branch in following repos:
https://github.com/avpatel/qemu.git
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
To enable ACLINT emulation on QEMU, use "-M virt,aclint=on"
instead of just "-M virt" in your QEMU command line. For now,
QEMU supports ACLINT only for virt machine.
Regards,
Anup
Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this require change in Table-1 privilege mode accesses? as well?
Should there also be a suggestion/recommendation on how to disable a pending interrupt (typically by writing to mtimecmp)?
On Thu, May 27, 2021 at 10:34 AM Neel Gala <neelgala@...> wrote:Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this require change in Table-1 privilege mode accesses? as well?Architecturally the 'time' CSR reads the same concept of "time" as the 'mtime' register. Simplistically the RDTIME pseudoinstruction reads what is in the 'mtime' register. One implementation is that each hart has a local copy of 'mtime' that is available to be read by RDTIME (in other words, copies of 'mtime' are distributed in hardware to each hart - to appear as the 'time' CSR inside each hart). Another implementation is to trap and emulate RDTIME using a read of the memory-mapped 'mtime' register. Other implementation approaches are possible.
Hi Neel,
You first question is already answered by Greg.
Regarding second question/suggestion, I agree we should explicitly state how to disable a pending interrupt.
Regards,
Anup
Sent: 27 May 2021 23:05
To: Anup Patel <Anup.Patel@...>
Cc: Josh Scheid <jscheid@...>; tech-aia@...; tech-unixplatformspec@...; Atish Patra <Atish.Patra@...>; Greg Favor <gfavor@...>; Alistair Francis <Alistair.Francis@...>; Andrew Waterman <andrew@...>; John Hauser <jh.riscv@...>
Subject: Re: [RISC-V] [tech-unixplatformspec] [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Hi,
Minor comments:
Should there be a mention that the user level "time" csr (0xC01) which is used by the rdtime pseudo-instruction will enable a read-only peek into the mtime register? Would this require change in Table-1 privilege mode accesses? as well?
Should there also be a suggestion/recommendation on how to disable a pending interrupt (typically by writing to mtimecmp)?
On Thu, May 27, 2021 at 10:45 AM Anup Patel <anup.patel@...> wrote:
Hi Josh,
I have created a GitHub PR addressing your comments. Please check if you are okay with this.
https://github.com/riscv/riscv-aclint/pull/2
Regards,
Anup
From: tech-aia@... <tech-aia@...> On Behalf Of Josh Scheid
Sent: 27 May 2021 01:58
To: Anup Patel <Anup.Patel@...>
Cc: tech-aia@...; tech-unixplatformspec@...; Atish Patra <Atish.Patra@...>; Greg Favor <gfavor@...>; Alistair Francis <Alistair.Francis@...>; Andrew Waterman <andrew@...>; John Hauser <jh.riscv@...>
Subject: Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Thanks for writing this up, Anup.
In https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc#24-synchronizing-multiple-mtimer-devices, the SW algorithm should include verifying the reference-target delta, retrying if the delta is out of bounds, and / or reporting failure to verify the synchronization is in bounds.
-Josh
On Tue, May 25, 2021 at 10:18 PM Anup Patel <anup.patel@...> wrote:
Hi All,
The RISC-V ACLINT specification is now hosted on RISC-V GitHub page:
https://github.com/riscv/riscv-aclint
https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc
Please review this at your end send feedback on AIA/Platform mailing
lists.
The RISC-V ACLINT specification is intended to be small and backward
compatible to the SiFive CLINT specification which makes existing
RISC-V platforms compliant with the RISC-V ACLINT specification.
Overall, from platforms specification perspective it complements
the RISC-V AIA specification by providing IPI and Timer functionality.
A complete functional implementation is available for QEMU RISC-V
along with OpenSBI and Linux RISC-V changes. Please refer, the
riscv_aclint_v1 branch in following repos:
https://github.com/avpatel/qemu.git
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
To enable ACLINT emulation on QEMU, use "-M virt,aclint=on"
instead of just "-M virt" in your QEMU command line. For now,
QEMU supports ACLINT only for virt machine.
Regards,
Anup
--
Neel Gala
Regarding second question/suggestion, I agree we should explicitly state how to disable a pending interrupt.