Does anyone know why the RV22A profile draft (https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc) mandates the following:
misa
If the H extension is supported then the H bit must be writable.
A RISC-V CPU with H hard-wired to 1 can still run any "correct" non-hypervisor software (e.g. a normal OS). Is there some compelling use case where non-hypervisor software wants to count on having the hypervisor extension disabled in hardware?
On the other hand, this requirement creates a substantial additional burden on the CPU design and verification. The CPU logic must include both "enabled" and "disabled" variants of every detail in the H extension, all of which have to be verified.
