Hi All, As noted previously I have a standing meeting that makes the previous Tues slot not work for me. Monday Feb 20 is a US holiday so we won't be meeting on Monday. Do any times work for others ne

Hi All, The OS-A SEE meeting will be Monday Feb 13 @ 9am PT. I now have a standing conflict on Tuesdays so I'll need to move these to Mondays all the time or we have to come up w/ a different time slo

Just to follow up from the last call we had, I filed https://github.com/riscv-non-isa/riscv-os-a-see/issues/4 to come up with the new naming for the “horizontal” and “vertical” recipes. Please take a

Hi All, I have to cancel the meeting today. However, if people want to use the meeting link feel free to use it and meet up. There's some structure put together in the spec repo: https://github.com/ri

Hi All, Sorry for the late reminder notice, but we'll be having our meeting Jan 31 @ 9am PT. -Aaron

Hi All, We'll be having an OS-A SEE Meeting Jan 24 @ 9am PT. Notes are published from previous meetings here. Please read Andrei's proposal and provide feedback. For this meeting I'd like to go over a

Hi All, Happy New Year. We'll be having an OS-A SEE Meeting Jan 10 @ 9am PT. See you then! Thanks. -Aaron

Hi All, We'll be meeting this coming Wed Nov 30 @ 9am PT. Link to join: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 We'll be going through Andrei's proposal which can be found he

Hi All, Based on feedback, below is the updated draft proposal of the SBI Debug Console Extension ... The motivations behind this proposal is as follows: 1) There is no new SBI extension replacing the

Hi All, We'll be having an OS-A SEE TG Meeting Nov 15 @ 9am PT. If there are specific topics people are interested in talking about please add them here. Thank you. -Aaron

Hi All, We'll be conducting an OS-A SEE TG meeting Nov 1st @ 9am PT. Link to join is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09

Hi All, We're having a OS-A SEE TG meeting tomorrow Oct 18 at 9am PT. We last met on Oct 4. The meeting slides can be found here. We did not get through everything as we had a discussion about scoping

Dear all, I just wanted to introduce myself and say ‘hi’. I recently joined the Intel SSE group as an engineer focusing on RISC-V standardization (in particular with an interest in collaborating on th

Hi All, This is a reminder that we'll be having the OS-A SEE meeting on October 4th at 9am Pacific Time. The join link is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Also,

Anup Patel <apatel@...> 于2022年7月14日周四 17:39写道： If I understand correctly, the N here should refer to the logical trigger, not the physical number. sbi needs to maintain these logic data, and this is r

You're right. There is a proposal at https://lists.riscv.org/g/sig-hypervisors/message/151 that will likely be implemented by Syntacore before the end of the year. Tim

To implement hardware breakpoints and watchpoints on the riscv, the trigger in M mode is required. We need an sbi extension for debugging to set the trigger. Please give suggestions and feedback. Rega

Hi All, Ved let me know I accidentally had a Google Meet Invite link. The Zoom meeting id is: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Thanks. -Aaron

Hi All, We had our first meeting this past Monday (2022/09/12). I pushed the notes to GitHub. As a reminder each group in RVI has their own folder for stashing collateral. For OS-A SEE TG, the folder

In the SiFive Core-Local Interruptor (CLINT) device , a core can access the mtimcmp register of all cores in the platform. In the ACLINT spec, If a platform implements multiple MTIMER devices, such as