Hi All, We'll be having an OS-A SEE Meeting Jan 24 @ 9am PT. Notes are published from previous meetings here. Please read Andrei's proposal and provide feedback. For this meeting I'd like to go over a

Hi All, Happy New Year. We'll be having an OS-A SEE Meeting Jan 10 @ 9am PT. See you then! Thanks. -Aaron

Hi All, We'll be meeting this coming Wed Nov 30 @ 9am PT. Link to join: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 We'll be going through Andrei's proposal which can be found he

Hi All, Based on feedback, below is the updated draft proposal of the SBI Debug Console Extension ... The motivations behind this proposal is as follows: 1) There is no new SBI extension replacing the

Hi All, We'll be having an OS-A SEE TG Meeting Nov 15 @ 9am PT. If there are specific topics people are interested in talking about please add them here. Thank you. -Aaron

Hi All, We'll be conducting an OS-A SEE TG meeting Nov 1st @ 9am PT. Link to join is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09

Hi All, We're having a OS-A SEE TG meeting tomorrow Oct 18 at 9am PT. We last met on Oct 4. The meeting slides can be found here. We did not get through everything as we had a discussion about scoping

Dear all, I just wanted to introduce myself and say ‘hi’. I recently joined the Intel SSE group as an engineer focusing on RISC-V standardization (in particular with an interest in collaborating on th

Hi All, This is a reminder that we'll be having the OS-A SEE meeting on October 4th at 9am Pacific Time. The join link is here: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Also,

Anup Patel <apatel@...> 于2022年7月14日周四 17:39写道： If I understand correctly, the N here should refer to the logical trigger, not the physical number. sbi needs to maintain these logic data, and this is r

You're right. There is a proposal at https://lists.riscv.org/g/sig-hypervisors/message/151 that will likely be implemented by Syntacore before the end of the year. Tim

To implement hardware breakpoints and watchpoints on the riscv, the trigger in M mode is required. We need an sbi extension for debugging to set the trigger. Please give suggestions and feedback. Rega

Hi All, Ved let me know I accidentally had a Google Meet Invite link. The Zoom meeting id is: https://zoom.us/j/2786028446?pwd=ZHFCR1JtKzg1WVpNZXNtci8xc1Mvdz09 Thanks. -Aaron

Hi All, We had our first meeting this past Monday (2022/09/12). I pushed the notes to GitHub. As a reminder each group in RVI has their own folder for stashing collateral. For OS-A SEE TG, the folder

In the SiFive Core-Local Interruptor (CLINT) device , a core can access the mtimcmp register of all cores in the platform. In the ACLINT spec, If a platform implements multiple MTIMER devices, such as

Hi All, Apologies for cross posting multiple lists. Just wanted to reach out to the maximum audience as this is a short notice to set up the first meeting. This is just a quick notice that the first P

Hi All, We are pleased to announce the early formation of Platform Runtime Services(PRS) Task Group with Atish Patra from Rivos as the acting chair and Sunil VL from ventana as the acting vice chair.

cross-posting for more visibility. ---------- Forwarded message --------- From: Atish Kumar Patra <atishp@...> Date: Thu, Sep 1, 2022 at 11:55 AM Subject: Call for Chair/Vice-Chair Candidates for Plat

Hi All, I put a meeting on the RISC-V calendar for Thursday September 1 @ 9am PT. I'll send the slides out earlier in the week for people to critique and add suggestions of topics. We'll go over the c

I don't think we should submit this one until we settle on how we convey behaviors outside of an ISA string. I suspect that will change so we should anticipate that. Right now we have ISA string plus