Hello everyone, This is a proposal to add Coffer Trusted Execution Environment(TEE) as a new member of SBI Implementations List. Coffer is a TEE implemented for RISC-V 32/64 systems. It utilizes the m

Hi All, The next platform HSC meeting is scheduled on Mon July 26th at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki Her

There are few ISA level requirements/strong recommendations that platform should follow. Create an new subsection to contain all these requirements. Move the user-level requirements from user.doc to h

There are few ISA level requirements/strong recommendations that platform should follow. Create an new subsection to contain all these requirements. Move the user-level requirements from user.doc to h

> The MTIME register is a 64-bit read-write register Is the device required to allow only 64-bit accesses to these registers? Can a device allow 32-bit accesses? Can a device only support 32-bit acces

This patch adds requirements for mapping PCIe interrupts to AIA. Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(

The first three details belong to a profile specification rather than platform spec. Remove those so that it can be included in the profile. The last remaining one belongs to platform spec but must be

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- Makefile | 18 +++-- pcie-topology.ditaa | 28 ++++++++ riscv-platform-spec.adoc

V5: - Improve text for PCIe cache coherency requirement. V4: - Fix Pcie cache coherency requirement to use 'No_Snoop bit' instead of 'No_snoop' - Removed empty section for peer-to-peer transactions V3

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- Makefile | 18 +++-- pcie-topology.ditaa | 28 ++++++++ riscv-platform-spec.adoc

Signed-off-by: Atish Patra <atish.patra@...> --- riscv-platform-spec.adoc | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/riscv-platform-spec.adoc b/riscv-platform

The platform and profile specification mean different things now. All the points specified in supervisor.adoc are already described in the new revamped platform spec. Remove these old specifications.

V4: - Fix Pcie cache coherency requirement to use 'No_Snoop bit' instead of 'No_snoop' - Removed empty section for peer-to-peer transactions V3: - Replaced references to PMA+PBMT by PMA - Moved the PC

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> --- Makefile | 18 +++-- pcie-topology.ditaa | 28 ++++++++ riscv-platform-spec.adoc

ACPI Requirement for OS-A Base Discovery mechanism. This requirement adds ACPI as an choice for discovery mechanism which firmware can implement. In case the firmware supports both Devicetree and ACPI

Hi All, The next platform HSC meeting is scheduled on Mon July 12th at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki Her

Signed-off-by: Atish Patra <atish.patra@...> --- riscv-platform-spec.adoc | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.ad

The first three details belong to a profile specification rather than platform spec. Remove those so that it can be included in the profile. The last remaining one belongs to platform spec but must be

The platform and profile specification mean different things now. All the points specified in supervisor.adoc are already described in the new revamped platform spec. Remove these old specifications.

V3: - Replaced references to PMA+PBMT by PMA - Moved the PCIe topology diagram to a separate adoc to enable it's inclusion into PDF V2: - Fixed abbreviation for root complex integrated endpoint - Adde