Signed-off-by: Kumar Sankaran <ksankaran@...> --- riscv-platform-spec.adoc | 42 ++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/riscv-platform-s

From: Abner Chang <abner.chang@...> As Atish mentioned in the meeting, resend the patch to this task group for the widely review becasue this document is referred in RISC-V platform spec. Abner Chang

Priv: """ Accesses by one hart to main memory regions are observable not only by other harts but also by other devices with the capability to initiate requests in the main memory system (e.g., DMA eng

This patch adds SBI direct memory access synchronize (DSYN)) extension which allows S-mode (or VS-mode) software to explicitly synchronize memory with assistance from the M-mode (or HS-mode). Signed-o

The proposal allows for prefetchable BARs to be programmed to support as I/O or Memory. This seems to conflict with the priv spec that states: """ Memory regions that do not fit into regular main memo

This patch adds requirements for PCIe support for the server extension Signed-off-by: Mayuresh Chitale <mchitale@...> Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec.adoc | 133

We have tagged the current SBI specification as a release candidate for v0.3[1]. It is tagged as v0.3-rc1 which includes few new extensions and cosmetic changes of the entire specification. Here is a

Hi All, The next platform HSC meeting is scheduled on Mon Jun 14th at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki Here

Hi All, The slides from today's AIA meeting are here: https://docs.google.com/presentation/d/1WHGm7ZpOkVlk_sAVYVU5UwBXt1cdH-8fM1s2vdpY6K4/edit?usp=sharing Both AIA and ACLINT specifications are now on

This is an initial patch for PCIe requirements for the server extension. The goal is to specify requirements for those PCIe elements which interact with the system such as PCIe config space, memory sp

Mention that an SBI extension shall not be partially implemented. Signed-off-by: Bin Meng <bmeng.cn@...> --- Changes in v2: - %s/a SBI/an SBI - reword the clarification riscv-sbi.adoc | 6 ++++++ 1 fil

Signed-off-by: Bin Meng <bmeng.cn@...> --- riscv-sbi.adoc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc index 11c30c3..8696f97 100644 --- a/riscv-sbi.adoc +++

From: Abner Chang <renba.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove CLINT from platf

This patch adds SBI performance monitoring unit (PMU) extension which allows S-mode (or VS-mode) software to configure hardware (or firmware) performance counters with help of M-mode (or HS-mode) soft

%s/secion/section/ %s/managment/management/ %s/implemenation/implementation/ %s/requestd/requested/ %s/hierarchial/hierarchical/ %s/inititated/initiated/ %s/recieves/receives/ %s/rententive/retentive/

%s/a SBI/an SBI/ %s/A SBI/An SBI/ Signed-off-by: Bin Meng <bmeng.cn@...> --- riscv-sbi.adoc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/riscv-sbi.adoc b/riscv-sbi.ad

Hi All, The next platform HSC meeting is scheduled on Fri Jun 4th at 8AM PST. This is a new slot only for this week due to Monday being a holiday in the US for Memorial Day and Wed being the RISC-V to

Signed-off-by: Paul Donahue pdonahue@... --- riscv-platform-spec.adoc | 101 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/riscv-platform-spec.adoc b/riscv-plat

Thanks for writing this up, Anup. In https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc#24-synchronizing-multiple-mtimer-devices, the SW algorithm should include verifying the referen

One other issue with the "mtime" synchronization by SW approach is that this effectively places an upper limit on the achievable timer unit resolution. It'd be some equation based on the ordered acces